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i.MX 8M Mini Applications Processor Datasheet for Consumer Products
i.MX 8M Mini Applications Processor Datasheet for Consumer Products
i.MX 8M Mini, MIMX8MM6DVTLZAA MIMX8MM5DVTLZAA, MIMX8MM5DVTLZCA, MIMX8MM5DVTLZDA, MIMX8MM4DVTLZAA, MIMX8MM3DVTLZAA, MIMX8MM2DVTLZAA, MIMX8MM1DVTLZAA
i.MX 8M Mini, MIMX8MM6DVTLZAA MIMX8MM5DVTLZAA, MIMX8MM5DVTLZCA, MIMX8MM5DVTLZDA..MIMX8MM4DVTLZAA, MIMX8MM3DVTLZAA..MIMX8MM2DVTLZAA, MIMX8MM1DVTLZAA
NXP Semiconductors
i.MX 8M Mini Applications Processor Datasheet for … – NXP
i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 4 NXP Semiconductors i.MX 8M Mini introduction NOTE The actual feature set depends on th e part numbers as described in Table 2 .
Evaluation Boards – Embedded – MCU, DSP – DIGITAL ELECTRONICS
NXP Semiconductors Data Sheet: Technical Data Document Number: IMX8MMCEC Rev. 1, 07/2020 MIMX8MM6DVTLZAA MIMX8MM5DVTLZCA MIMX8MM4DVTLZAA MIMX8MM2DVTLZAA MIMX8MM5DVTLZAA MIMX8MM5DVTLZDA MIMX8MM3DVTLZAA MIMX8MM1DVTLZAA i.MX 8M Mini Applications Processor Datasheet for Consumer Products Package Information Plastic Package FCBGA 14 x 14 mm, 0.5 mm pitch Ordering Information See Table 2 on page 6 1 i.MX 8M Mini introduction The i.MX 8M Mini applications processor represents 1. i.MX 8M Mini introduction . . . . . . . . . . . . . . . . . . . . . . . . 1 NXP’s latest video and audio experience combining 1.1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 state-of-the-art media-specific features with 2. 1.2. Ordering information . . . . . . . . . . . . . . . . . . . . . . . 6 Modules list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 high-performance processing while optimized for lowest 2.1. Recommended connections for unused input/output 12 power consumption. 3. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1. Chip-level conditions . . . . . . . . . . . . . . . . . . . . . . 14 The i.MX 8M Mini family of processors features advanced implementation of a quad Arm� Cor- 3.2. Power supplies requirements and restrictions . . . 23 3.3. PLL electrical characteristics . . . . . . . . . . . . . . . . 26 3.4. On-chip oscillators . . . . . . . . . . . . . . . . . . . . . . . . 27 tex�-A53 core, which operates at speeds of up to 3.6. I/O AC parameters . . . . . . . . . . . . . . . . . . . . . . . 29 3.5. General purpose I/O (GPIO) DC parameters . . . 28 1.8 GHz. A general purpose Cortex�-M4 400 MHz core processor is for low-power processing. The DRAM 3.7. Output buffer impedance parameters . . . . . . . . . 30 3.8. System modules timing . . . . . . . . . . . . . . . . . . . . 32 3.9. External peripheral interface parameters . . . . . . 33 controller supports 32-bit/16-bit LPDDR4, DDR4, and 4. Boot mode configuration . . . . . . . . . . . . . . . . . . . . . . . . 68 4.1. Boot mode configuration pins . . . . . . . . . . . . . . . 68 DDR3L memory. A wide range of audio interfaces are 4.2. Boot device interface allocation . . . . . . . . . . . . . . 69 available, including I2S, AC97, TDM, and S/PDIF. 5. Package information and contact assignments . . . . . . . 70 5.1. 14 x 14 mm package information . . . . . . . . . . . . 70 There are a number of other interfaces for connecting 5.2. DDR pin function list . . . . . . . . . . . . . . . . . . . . . . 87 peripherals, such as USB, PCIe, and Ethernet. 6. Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products. i.MX 8M Mini introduction Subsystem Arm Cortex-A53 MPCore platform Arm Cortex-M4 core platform Connectivity On-chip memory GPIO and pin multiplexing Power management Table 1. Features Features Quad symmetric Cortex-A53 processors � 32 KB L1 Instruction Cache � 32 KB L1 Data Cache � Media Processing Engine (MPE) with NEON technology supporting the Advanced Single Instruction Multiple Data architecture: � Floating Point Unit (FPU) with support of the VFPv4-D16 architecture Support of 64-bit Armv8-A architecture 512 KB unified L2 cache Low power microcontroller available for customer application: � low power standby mode � IoT features including Weave � Manage IR or Wireless Remote Cortex M4 CPU: � 16 KB L1 Instruction Cache � 16 KB L1 Data Cache � 256 KB tightly coupled memory (TCM) One PCI Express (PCIe) � Single lane supporting PCIe Gen2 � Dual mode operation to function as root complex or endpoint � Integrated PHY interface � Support L1 low power sub-state Two USB 2.0 OTG controllers with integrated PHY interfaces: � Spread spectrum clock support Three Ultra Secure Digital Host Controller (uSDHC) interfaces: � MMC 5.1 compliance with HS400 DDR signaling to support up to 400 MB/sec � SD/SDIO 3.0 compliance with 200 MHz SDR signaling to support up to 100 MB/sec � Support for SDXC (extended capacity) One Gigabit Ethernet controller with support for Energy Efficient Ethernet (EEE), Ethernet AVB, and IEEE 1588 Four Universal Asynchronous Receiver/Transmitter (UART) modules Four I2C modules Three ECSPI modules Boot ROM (256 KB) On-chip RAM (256 KB + 32 KB) General-purpose input/output (GPIO) modules with interrupt capability Input/output multiplexing controller (IOMUXC) to provide centralized pad control Temperature sensor with programmable trip points Flexible power domain partitioning with internal power switches to support efficient power management i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 2 NXP Semiconductors Subsystem External memory interface Multimedia System debug i.MX 8M Mini introduction Table 1. Features (continued) Features 32/16-bit DRAM interfaces: � LPDDR4 (up to 1.5 GHz) � DDR4-2400 � DDR3L-1600 8-bit NAND-Flash, including support for Raw MLC/SLC devices, BCH ECC up to 62-bit, and ONFi3.2 compliance (clock rates up to 100 MHz and data rates up to 200 MB/sec) eMMC 5.1 Flash (2 interfaces, uSDHC1 and uSDHC3) SPI NOR Flash (3 interfaces) FlexSPI with support for XIP (for ME in low-power mode) and parallel read mode of two identical FLASH devices Video Processing Unit: � 1080p60 VP9 Profile 0, 2 (10-bit) � 1080p60 HEVC/H.265 Decoder � 1080p60 AVC/H.264 Baseline, Main, High decoder � 1080p60 VP8 � 1080p60 AVC/H.264 Encoder � 1080p60 VP8 � TrustZone support Graphic Processing Unit: � GCNanoUltra for 3D acceleration � GC320 for 2D acceleration LCDIF Display Controller: � Support up to 2 layers of overlay � Support up to 1080p60 display through MIPI DSI MIPI Interface: � 4-lane MIPI CSI interface � 4-lane MIPI DSI interface Audio: � S/PDIF input and output, including a new Raw Capture input mode � Five synchronous audio interface (SAI) modules supporting I2S, AC97, TDM, codec/DSP, and DSD interfaces, including one SAI with 8 Tx and 8 Rx lanes, one SAI with 4 Tx and 4 Rx lanes, two SAI with 2 Tx and 2 Rx lanes, and one SAI with 1 Tx and 1Rx lane. Support over 20 channels of audio subject to I/O limitations. � 8-Channel Pulse Density Modulation (PDM) input Arm CoreSight debug and trace architecture Trace Port Interface Unit (TPIU) to support off-chip real-time trace Embedded Trace FIFO (ETF) with 4 KB internal storage to provide trace buffering Unified trace capability for Quad Cortex-A53 and Cortex-M4 CPUs Cross Triggering Interface (CTI) Support for 5-pin (JTAG) debug interface i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 NXP Semiconductors 3 i.MX 8M Mini introduction Table 1. Features (continued) Subsystem Features Security Resource Domain Controller (RDC) supports four domains and up to eight regions of DDR Arm TrustZone (TZ) architecture: � Support Arm Cortex-A53 MPCore TrustZone On-chip RAM (OCRAM) secure region protection using OCRAM controller High Assurance Boot (HAB) Cryptographic acceleration and assurance (CAAM) module and Assurance Module: � Support Widevine and PlayReady content protection � Public Key Cryptography (PKHA) with RSA and Elliptic Curve (ECC) algorithms � Real-time integrity checker (RTIC) � DRM support for RSA, AES, 3DES, DES � Side channel attack resistance � True random number generation (RNG) � Manufacturing protection support Secure non-volatile storage (SNVS): � Secure real-time clock (RTC) Secure JTAG controller (SJC) NOTE The actual feature set depends on the part numbers as described in Table 2. Functions such as display and camera interfaces, and connectivity interfaces, may not be enabled for specific part numbers. i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 4 NXP Semiconductors i.MX 8M Mini introduction 1.1 Block diagram Figure 1 shows the functional modules in the i.MX 8M Mini applications processor system. Security TrustZone DRM Ciphers Secure Clock eFuse Key Storage Random Number 32 KB Secure RAM System Control 3x Smart DMA XTAL PLLs 3x Watchdog 4x PWM 6x Timer Secure JTAG Temperature Sensor Main CPU Platform Quad Cortex-A53 32 KB I-cache 32 KB D-cache NEON FPU 512 KB L2 Cache Low Power, Security CPU Cortex-M4 16 KB I-cache 16 KB D-cache 256 KB TCM Multimedia 3D Graphics: GC NanoUltra 2D Graphics: GC320 1080p60 H265, VP9 decoder 1080p60 H264, VP8 decoder 1080p60 H.264, VP8 encoder 4-lane MIPI-CSI Interface 4-lane MIPI-DSI Interface Connectivity and I/O 1 GB Ethernet (IEEE1588, EEE, and AVB) S/PDIF Rx and Tx 5x I2S/SAI 2x USB 2.0 OTG and PHY 1x PCIe 2.0 (1-lane) 4x UART 4x I2C, 3x ECSPI PDM External Memory LPDDR4/DDR4/DDR3L 2x eMMC 5.1/3x SD 3.0 NAND CTL (BCH62) 1x FlexSPI Figure 1. i.MX 8M Mini system block diagram i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 NXP Semiconductors 5 i.MX 8M Mini introduction 1.2 Ordering information Table 2 shows examples of orderable sample part numbers covered by this data sheet. This table does not include all possible orderable part numbers. If your desired part number is not listed in the table, or you have questions about available parts, contact your NXP representative. Table 2. Orderable part numbers Family Part number Part differentiator Cortex-A53 CPU speed grade Qualification tier Temperat ure Tj (C) Package i.MX 8M Mini MIMX8MM6DVTLZAA 4x A53, M4, GPU, VPU 1.8 GHz Quad Consumer 0 to +95 14 x 14 mm, 0.5 mm pitch i.MX 8M Mini MIMX8MM5DVTLZAA QuadLite 4x A53, M4, GPU 1.8 GHz Consumer 0 to +95 14 x 14 mm, 0.5 mm pitch i.MX 8M Mini MIMX8MM5DVTLZCA 4x A53, M4, GPU, QuadLite Immersiv3D with Dolby ATMOS support1 1.8 GHz Consumer 0 to +95 14 x 14 mm, 0.5 mm pitch i.MX 8M Mini QuadLite MIMX8MM5DVTLZDA 4x A53, M4, GPU, Immersiv3D with Dolby ATMOS and DTS support1 1.8 GHz Consumer 0 to +95 14 x 14 mm, 0.5 mm pitch i.MX 8M Mini MIMX8MM4DVTLZAA 2x A53, M4, GPU, VPU 1.8 GHz Dual Consumer 0 to +95 14 x 14 mm, 0.5 mm pitch i.MX 8M Mini MIMX8MM3DVTLZAA DualLite 2x A53, M4, GPU 1.8 GHz Consumer 0 to +95 14 x 14 mm, 0.5 mm pitch i.MX 8M Mini MIMX8MM2DVTLZAA 1x A53, M4, GPU, VPU 1.8 GHz Solo Consumer 0 to +95 14 x 14 mm, 0.5 mm pitch i.MX 8M Mini MIMX8MM1DVTLZAA SoloLite 1x A53, M4, GPU 1.8 GHz Consumer 0 to +95 14 x 14 mm, 0.5 mm pitch 1 Supply of this Implementation of Dolby technology does not convey a license nor imply a right under any patent, or any other industrial or intellectual property right of Dolby Laboratories, to use this Implementation in any finished end-user or ready-to-use final product. It is hereby notified that a license for such use is required from Dolby Laboratories. Figure 2 describes the part number nomenclature so that the users can identify the characteristics of the specific part number. Contact an NXP representative for additional details. i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 6 NXP Semiconductors i.MX 8M Mini introduction MIMX8MM@+VT$$%A Qualification level Part number series Part differentiator Silicon revision Fusing options Primary core frequency Package type � all ROHS Qualification tier Tj Qualification Level Samples P Mass Production M Part number series IMX8MM Name i.MX 8M Mini Part differentiator @ i.MX 8M Mini Quad 6 4x A53, M4, GPU, VPU i.MX 8M Mini QuadLite 5 4x A53, M4, GPU i.MX 8M Mini Dual 4 2x A53, M4, GPU, VPU i.MX 8M Mini DualLite 3 2x A53, M4, GPU i.MX 8M Mini Solo 2 1x A53, M4, GPU, VPU i.MX 8M Mini SoloLite 1 1x A53, M4, GPU Temperature Tj Consumer: 0 to +95oC Industrial: -40 to 105oC Package Type FCBGA486 14 x 14 mm, 0.5 mm pitch + Frequency $$ D 1.8 GHz LZ C 1.6 GHz KZ ROHS Fusing % VT Default A Immersiv3D enabled w/Dolby Atmos C Immersiv3D enabled w/Dolby Atmos D and DTS Silicon rev A Rev A0 A Figure 2. Part number nomenclature–i.MX 8M Mini family of processors i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 NXP Semiconductors 7 Modules list 2 Modules list The i.MX 8M Mini family of processors contains a variety of digital and analog modules. Table 3 describes these modules in alphabetical order. Table 3. i.MX 8M Mini modules list Block mnemonic Block name Brief description 32k Oscillator APBH-DMA Arm BCH CAAM CCM GPC SRC CSU CTI-0 CTI-1 CTI-2 CTI-3 CTI-4 DAP DDRC eCSPI1 eCSPI2 eCSPI3 Clock system 32 KHz oscillator is used as the clock source for RTC and internal low speed clock. It can be supplied by external 32.768 KHz oscillator. NAND Flash and BCH ECC DMA controller used for GPMI2 operation. DMA Controller Arm Platform The Arm Core Platform includes a quad Cortex-A53 core and a Cortex-M4 core. The Cortex-A53 core includes associated sub-blocks, such as the Level 2 Cache Controller, Snoop Control Unit (SCU), General Interrupt Controller (GIC), private timers, watchdog, and CoreSight debug modules. The Cortex-M4 core is used as a customer microcontroller. Binary-BCH ECC Processor The BCH module provides up to 62-bit ECC encryption/decryption for NAND Flash controller (GPMI) Cryptographic accelerator and assurance module CAAM is a cryptographic accelerator and assurance module. CAAM implements several encryption and hashing functions, a run-time integrity checker, entropy source generator, and a Pseudo Random Number Generator (PRNG). The PRNG is certifiable by the Cryptographic Algorithm Validation Program (CAVP) of the National Institute of Standards and Technology (NIST). CAAM also implements a Secure Memory mechanism. In i.MX 8M Mini processors, the secure memory provided is 32 KB. Clock Control Module, General These modules are responsible for clock and reset distribution in the Power Controller, System Reset system, and also for the system power management. Controller Central Security Unit The Central Security Unit (CSU) is responsible for setting comprehensive security policy within the i.MX 8M Mini platform. Cross Trigger Interface Cross Trigger Interface (CTI) allows cross-triggering based on inputs from masters attached to CTIs. The CTI module is internal to the Cortex-A53 core platform. Debug Access Port Double Data Rate Controller Configurable SPI The DAP provides real-time access for the debugger without halting the core to access: � System memory and peripheral registers � All debug configuration registers The DAP also provides debugger access to JTAG scan chains. The DDR Controller has the following features: � Supports 32/16-bit LPDDR4 (up to 1.5 GHz), DDR4-2400, and DDR3L-1600 � Supports up to 8 Gbyte DDR memory space Full-duplex enhanced Synchronous Serial Interface, with data rate up to 52 Mbit/s. Configurable to support Master/Slave modes, only one chip select is supported. i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 8 NXP Semiconductors Block mnemonic ENET1 FlexSPI GIC GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPMI GPT1 GPT2 GPT3 GPT4 GPT5 GPT6 GPU3D I2C1 I2C2 I2C3 I2C4 IOMUXC Modules list Table 3. i.MX 8M Mini modules list (continued) Block name Brief description Ethernet Controller The Ethernet Media Access Controller (MAC) is designed to support 10/100/1000 Mbps Ethernet/IEEE 802.3 networks. An external transceiver interface and transceiver function are required to complete the interface to the media. The module has dedicated hardware to support the IEEE 1588 standard. See the ENET chapter of the i.MX 8M Mini Applications Processor Reference Manual (IMX8MMRM) for details. FlexSPI The FlexSPI module acts as an interface to external serial flash devices. This module contains the following features: � Flexible sequence engine to support various flash vendor devices � Single pad/Dual pad/Quad pad mode of operation � Single Data Rate/Double Data Rate mode of operation � Parallel Flash mode � DMA support � Memory mapped read access to connected flash devices � Multi master access with priority and flexible and configurable buffer for each master Generic Interrupt Controller The GIC handles all interrupts from the various subsystems and is ready for virtualization. General Purpose I/O Modules Used for general purpose input/output to external ICs. Each GPIO module supports up to 32 bits of I/O. General Purpose Memory Interface The GPMI module supports up to 8x NAND devices and 62-bit ECC encryption/decryption for NAND Flash Controller (GPMI2). GPMI supports separate DMA channels for each NAND device. General Purpose Timer Each GPT is a 32-bit “free-running” or “set-and-forget” mode timer with programmable prescaler and compare and capture register. A timer counter value can be captured using an external event and can be configured to trigger a capture event on either the leading or trailing edges of an input pulse. When the timer is configured to operate in “set-and-forget” mode, it is capable of providing precise interrupts at regular intervals with minimal processor intervention. The counter has output compare logic to provide the status and interrupt at comparison. This timer can be configured to run either on an external clock or on an internal clock. Graphics Processing Unit-3D I2C Interface The GPU3D provides hardware acceleration for 3D graphics algorithms with sufficient processor power to run desktop quality interactive graphics applications on displays. I2C provides serial interface for external devices. Data rates of up to 320 kbps are supported. IOMUX Control This module enables flexible I/O multiplexing. Each IO pad has a default as well as several alternate functions. The alternate functions are software configurable. i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 NXP Semiconductors 9 Modules list Table 3. i.MX 8M Mini modules list (continued) Block mnemonic Block name Brief description MIPI CSI2 (four-lane) MIPI DSI (four-lane) OCOTP_CTRL OCRAM PCIe1 PDM PMU PWM1 PWM2 PWM3 PWM4 SAI1 SAI2 SAI3 SAI5 SAI6 MIPI Camera Serial Interface This module provides one four-lane MIPI camera serial interfaces, which operates up to a maximum bit rate of 1.5 Gbps. MIPI Display Serial Interface This module provides a four-lane MIPI display serial interface operating up to a maximum bit rate of 1.5 Gbps. OTP Controller The On-Chip OTP controller (OCOTP_CTRL) provides an interface for reading, programming, and/or overriding identification and control information stored in on-chip fuse elements. The module supports electrically programmable poly fuses (eFUSEs). The OCOTP_CTRL also provides a set of volatile software-accessible signals that can be used for software control of hardware elements, not requiring non volatility. The OCOTP_CTRL provides the primary user-visible mechanism for interfacing with on-chip fuse elements. Among the uses for the fuses are unique chip identifiers, mask revision numbers, cryptographic keys, JTAG secure mode, boot characteristics, and various control signals requiring permanent non volatility. On-Chip Memory controller The On-Chip Memory controller (OCRAM) module is designed as an interface between the system’s AXI bus and the internal (on-chip) SRAM memory module. In i.MX 8M Mini processors, the OCRAM is used for controlling the 256 KB multimedia RAM through a 64-bit AXI bus. PCI Express 2.0 The PCIe IP provides PCI Express Gen 2.0 functionality. Pulse Density Modulation The PDM supports up to 8-channels (4 lanes). Power Management Unit Integrated power management unit. Used to provide power to various SoC domains. Pulse Width Modulation The pulse-width modulator (PWM) has a 16-bit counter and is optimized to generate sound from stored sample audio images. It can also generate tones. It uses 16-bit resolution and a 4×16 data FIFO to generate sound. Synchronous Audio Interface The SAI module provides a synchronous audio interface (SAI) that supports full duplex serial interfaces with frame synchronization, such as I2S, AC97, TDM, and codec/DSP interfaces. i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 10 NXP Semiconductors Block mnemonic SDMA SJC SNVS SPDIF1 TEMPSENSOR TZASC Modules list Table 3. i.MX 8M Mini modules list (continued) Block name Brief description Smart Direct Memory Access The SDMA is a multichannel flexible DMA engine. It helps in maximizing system performance by offloading the various cores in dynamic data routing. It has the following features: � Powered by a 16-bit Instruction-Set micro-RISC engine � Multi channel DMA supporting up to 32 time-division multiplexed DMA channels � 48 events with total flexibility to trigger any combination of channels � Memory accesses including linear, FIFO, and 2D addressing � Shared peripherals between Arm and SDMA � Very fast Context-Switching with 2-level priority based preemptive multi tasking � DMA units with auto-flush and prefetch capability � Flexible address management for DMA transfers (increment, decrement, and no address changes on source and destination address) � DMA ports can handle unidirectional and bidirectional flows (Copy mode) � Up to 8-word buffer for configurable burst transfers for EMIv2.5 � Support of byte-swapping and CRC calculations � Library of Scripts and API is available Secure JTAG Controller The SJC provides JTAG interface (designed to be compatible with JTAG TAP standards) to internal logic. The i.MX 8M Mini family of processors uses JTAG port for production, testing, and system debugging. Additionally, the SJC provides BSR (Boundary Scan Register) standard support, designed to be compatible with IEEE 1149. 1. The JTAG port must be accessible during platform initial laboratory bring-up, for manufacturing tests and troubleshooting, as well as for software debugging by authorized entities. The i.MX 8M Mini SJC incorporates three security modes for protecting against unauthorized accesses. Modes are selected through eFUSE configuration. Secure Non-Volatile Storage Secure Non-Volatile Storage, including Secure Real Time Clock, Security State Machine, Master Key Control, and Violation/Tamper Detection and reporting. Sony Philips Digital Interconnect Format A standard audio file transfer format, developed jointly by the Sony and Phillips corporations. It supports Transmitter and Receiver functionality. Temperature Sensor Temperature sensor Trust-Zone Address Space Controller The TZASC (TZC-380 by Arm) provides security address region control functions required for intended application. It is used on the path to the DRAM controller. i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 NXP Semiconductors 11 Modules list Block mnemonic UART1 UART2 UART3 UART4 uSDHC1 uSDHC2 uSDHC3 USB1 USB2 VPU WDOG1 WDOG2 WDOG3 XTALOSC Table 3. i.MX 8M Mini modules list (continued) Block name Brief description UART Interface Each of the UARTv2 modules supports the following serial data transmit/receive protocols and configurations: � 7- or 8-bit data words, 1 or 2 stop bits, programmable parity (even, odd, or none) � Programmable baud rates up to 4 Mbps. This is a higher max baud rate relative to the 1.875 MHz, which is stated by the TIA/EIA-232-F standard. � 32-byte FIFO on Tx and 32 half-word FIFO on Rx supporting auto-baud SD/MMC and SDXC Enhanced Multi-Media Card / Secure Digital Host Controller i.MX 8M Mini SoC characteristics: All the MMC/SD/SDIO controller IPs are based on the uSDHC IP. They are designed to support: � SD/SDIO standard, up to version 3.0. � MMC standard, up to version 5.1. � 1.8 V and 3.3 V operation, but do not support 1.2 V operation. � 1-bit/4-bit SD and SDIO modes, 1-bit/4-bit/8-bit MMC mode. Two uSDHC controllers (uSDHC1 and uSDHC3) can support up to an 8-bit interface, the other controller (uSDHC2) can only support up to a 4-bit interface. 2x USB 2.0 controllers and PHYs Two USB controllers and PHYs that support USB 2.0. Each USB instance contains: � USB 2.0 core, which can operate in 2.0 mode Video Processing Unit A high performing video processing unit (VPU), which covers many SD-level and HD-level video decoders. See the i.MX 8M Mini Applications Processor Reference Manual (IMX8MMRM) for a complete list of the VPU’s decoding and encoding capabilities. Watchdog The watchdog (WDOG) timer supports two comparison points during each counting period. Each of the comparison points is configurable to evoke an interrupt to the Arm core, and a second point evokes an external event on the WDOG line. Crystal Oscillator interface The XTALOSC module enables connectivity to an external crystal oscillator device. In a typical application use case, it is used for a 24 MHz oscillator. 2.1 Recommended connections for unused input/output If a function of the i.MX 8M Mini is not in use, the I/Os and power rails of that function can be terminated to reduce overall board power. Table 4 shows the recommended connections for unused power supply rails. Table 4. Recommended connections for unused power supply rails Function Ball Name MIP-CSI and MIPI-DSI PCIe VDD_MIPI_0P9, VDD_MIPI_1P2, VDD_MIPI_1P8 VDD_PCI_0P8, VDD_PCI_1P8 Recommendations if Unused Leave unconnected Leave unconnected i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 12 NXP Semiconductors Modules list Table 4. Recommended connections for unused power supply rails (continued) Function Ball Name Recommendations if Unused USB1 and USB2 VDD_USB_0P8, VDD_USB_1P8, VDD_USB_3P3 Leave unconnected VPU VDD_VPU Leave unconnected GPU VDD_GPU Leave unconnected Digital I/O supplies NVCC_CLK, NVCC_ECSPI, NVCC_ENET, NVCC_GPIO1, NVCC_I2C, All digital I/O NVCC_JTAG, NVCC_NAND, NVCC_SAI1, NVCC_SAI2, NVCC_SAI3, NVCC_SAI5, supplies listed in this NVCC_SD1, NVCC_SD2, NVCC_UART, NVCC_SNVS_1P8, PVCC0_1P8, table must be PVCC1_1P8, PVCC2_1P8 powered under normal conditions whether the associated I/O pins are in use or not, and associated I/O pins need to enable pull in pad control register to limit any floating gate current. Table 5 shows recommended connections for unused signal contacts/interfaces. Table 5. Recommended connections for unused signal contacts/interfaces Function MIPI-CSI Ball Name MIPI_CSI_CLK_P, MIPI_CSI_CLK_N, MIPI_CSI_Dx_P, MIPI_CSI_Dx_N MIPI-DSI PCIe USB1 USB2 MIPI_VREG_CAP, MIPI_DSI_CLK_P, MIPI_DSI_CLK_N, MIPI_DSI_Dx_P, MIPI_DSI_Dx_N PCIE_CLK_P, PCIE_CLK_N, PCIE_TXN_P, PCIE_TXN_N, PCIE_RXN_P, PCIE_RXN_N, PCIE_RESREF USB1_VBUS, USB1_DN, USB1_DP, USB1_ID, USB1_TXRTUNE USB2_VBUS, USB2_DN, USB2_DP, USB2_ID, USB2_TXRTUNE Recommendations if Unused Tie all signals to ground Leave unconnected Leave unconnected Leave unconnected Leave unconnected i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 NXP Semiconductors 13 Electrical characteristics 3 Electrical characteristics This section provides the device and module-level electrical characteristics for the i.MX 8M Mini family of processors. 3.1 Chip-level conditions This section provides the device-level electrical characteristics for the IC. See Table 6 for a quick reference to the individual tables and sections. Table 6. i.MX 8M Mini chip-level conditions For these characteristics, … Topic appears … Absolute maximum ratings FCBGA package thermal resistance Operating ranges External clock sources Maximum supply currents on page 14 on page 16 on page 17 on page 19 on page 20 3.1.1 Absolute maximum ratings CAUTION Stresses beyond those listed under Table 7 may affect reliability or cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated in the operating ranges or parameters tables is not implied. Table 7. Absolute maximum ratings Parameter description Symbol Min Max Unit Core supply voltages Power supply for GPU Power supply for VPU DDR PHY supply voltage DDR I/O supply voltage DRAM PLL supply voltage SNVS IO supply voltage VDD_SNVS supply voltage VDD_ARM -0.3 VDD_SOC VDD_GPU -0.3 VDD_VPU -0.3 VDD_DRAM -0.3 NVCC_DRAM -0.3 VDD_DRAM_PLL_0P8 -0.3 VDD_DRAM_PLL_1P8 -0.3 NVCC_SNVS_1V8 -0.3 VDD_SNVS_0V8 -0.3 1.15 V 1.15 V 1.15 V 1.15 V 1.575 V 1.15 V 2.15 V 2.15 V 0.95 V Notes — — — — — — — — — i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 14 NXP Semiconductors Electrical characteristics Table 7. Absolute maximum ratings (continued) Parameter description Symbol Min Max Unit Notes GPIO supply voltage NVCC_JTAG, -0.3 3.8 V — NVCCGPIO1, NVCC_ENET, NVCC_SD1, NVCC_SD2, NVCC_NAND, NVCC_SA1, NVCC_SAI2, NVCC_SAI3, NVCC_SAI5, NVCC_ECSPI, NVCC_I2C, NVCC_UART, NVCC_CLK GPIO pre-driver supply voltage PVCC0_1P8, -0.3 2.15 V — PVCC1_1P8, PVCC2_1P8 Isolated core supply voltage VDD_ANA_0P8 -0.3 1.15 V — Analog core supply voltage VDD_ANA0_1P8 -0.3 2.15 V — VDD_ANA1_1P8 -0.3 2.15 V — Arm PLL supply voltage VDD_ARM_PLL_0P8 -0.3 0.95 V — VDD_ARM_PLL_1P8 -0.3 2.15 V — VDD_MIPI_0P9 -0.3 1.05 V — MIPI PHY supply voltage VDD_MIPI_1P2 -0.3 1.45 V — VDD_MIPI_1P8 -0.3 2.15 V — PCIe PHY supply voltage VDD_PCIE_0P8 -0.3 0.95 V — VDD_PCIE_1P8 -0.3 2.15 V — VDD_USB_0P8 -0.3 0.95 V — USB PHY supply voltage VDD_USB_1P8 -0.3 2.15 V — VDD_USB_3P3 -0.3 3.95 V — USB_VBUS input detected USB1_VBUS, -0.3 3.95 V — USB2_VBUS XTAL supply voltage VDD_24M_XTAL_1P8 -0.3 2.15 V — Storage temperature range TSTORAGE -40 150 oC — i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 NXP Semiconductors 15 Electrical characteristics Table 8. Electrostatic discharge and latch up ratings Parameter description Rating Reference Electrostatic Discharge (ESD) Latch UP (LU) Human Body Model (HBM) Charged Device Model (CDM) Immunity level: � Class I@ 25 oC ambient temperature � Class II @ 105 oC ambient temperature �1000 V �250 V JS-001-2017 JS-002-2018 A JESD78E A Comment — — — 3.1.2 Thermal resistance 3.1.2.1 FCBGA package thermal resistance Table 9 displays the FCBGA package thermal resistance data. Table 9. Thermal resistance data Rating Test conditions Symbol Value Unit Notes Junction to Ambient Natural Convection Single layer board (1s) RJA 30 oC/W 1, 2 Junction to Ambient Natural Convection Four layer board (2s2p) RJA 22.9 oC/W 1, 2, 3 Junction to Ambient (@200 ft/min) Single layer board (1s) RJMA 24 oC/W 1, 3 Junction to Ambient (@200 ft/min) Four layer board (2s2p) RJMA 18.5 oC/W 1, 3 Junction to Board — RJB 7.8 oC/W 4 Junction to Case — RJC 4 oC/W 5 Junction to Package Top Natural Convection JT 0.2 oC/W 6 1 Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2 Per SEMI G38-87 and JESD51-2 with the single layer board horizontal. 3 Per JEDEC JESD51-6 with the board horizontal. 4 Thermal resistance between the die and printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 5 Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 6 Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 16 NXP Semiconductors Electrical characteristics 3.1.3 Operating ranges Table 10 provides the operating ranges of the i.MX 8M Mini applications processor. For details on the chip’s power structure, see the “Power Management Unit (PMU)” chapter of the i.MX 8M Mini Applications Processor Reference Manual (IMX8MMRM). Table 10. Operating ranges1 Symbol Min Typ Max2,3 Unit Comment VDD_ARM VDD_SOC without PCIE VDD_SOC with PCIE VDD_GPU VDD_VPU VDD_DRAM VDD_SNVS_0P8 NVCC_SNVS_1P8 NVCC_JTAG, NVCC_GPIO1, NVCC_ENET, NVCC_SD1, NVCC_SD2, NVCC_NAND, NVCC_SAI1, NVCC_SAI2, NVCC_SAI3, NVCC_SAI5, NVCC_ECSPI, NVCC_I2C, NVCC_UART, NVCC_CLK NVCC_ENET 0.805 0.900 0.950 0.780 0.805 0.805 0.855 — 0.805 0.855 0.900 0.805 0.855 0.900 0.760 1.620 1.650 3.000 2.250 0.850 0.950 1.000 0.820 0.850 0.850 0.900 — 0.850 0.900 0.950 0.850 0.900 0.950 0.800 1.800 1.800 3.300 2.500 0.950 1.000 1.050 0.900 0.900 0.900 1.000 — 0.900 0.950 1.000 0.900 0.950 1.000 0.900 1.980 1.950 3.600 V Power supply for Quad-A53, 1.2 GHz V Power supply for Quad-A53, 1.6 GHz V Power supply for Quad-A53, 1.8 GHz4 V Power supply for SoC logic5 V Power supply for SoC logic5 V Power supply for 3D GPU, nominal mode, 800 MHz V Power supply for 3D GPU, overdrive mode, 1000 MHz — Block G2/G1/H1 V Power supply for VPU, 450/450/450 MHz V Power supply for VPU, 600/650/650 MHz V Power supply for VPU, 700/750/750 MHz V Power supply for DDRC, 0.85 V supports up to 1.0 GHz (DDR clock) V Power supply for DDRC, 0.9 V supports up to 1.2 GHz (DDR clock) V Power supply for DDRC, 0.95 V supports up to 1.5 GHz (DDR clock) V Power supply for SNVS core logic V Power supply for GPIO pre-driver in SNVS bank V Power supply for GPIO when it is in 1.8 V mode V Power supply for GPIO when it is in 3.3 V mode 2.750 V Power supply for GPIO when it is in 2.5 V mode i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 NXP Semiconductors 17 Electrical characteristics Symbol Table 10. Operating ranges1 (continued) Min Typ Max2,3 Unit Comment PVCC0_1P8, PVCC1_1P8, PVCC2_1P8 1.650 1.800 1.950 V Power supply for GPIO pre-driver VSS — — — V Ground for all core logic and I/O NVCC_DRAM 1.283 1.35 1.425 V DDR3L 1.14 1.2 1.26 V DDR4 1.06 1.1 1.17 V LPDDR4 DRAM_VREF 0.49 x 0.5 x 0.51 x V Internal output, no connection is needed. NVCC_DRAM NVCC_DRAM NVCC_DRAM VDD_DRAM_PLL_0P8 0.805 0.850 1.000 V 0.8 V logic power supply for DSM. It should be connected to the separate logic power. VDD_ANA0_1P8 1.71 1.8 1.89 V Analog 1.8 V core power VDD_ANA1_1P8 VDD_ANA_0P8 0.780 0.820 0.900 V Isolated 0.8 V core power VDD_ARM_PLL_0P8 0.780 0.820 0.900 V Arm PLL 0.8 V power VDD_ARM_PLL_1P8 1.71 1.8 1.89 V Arm PLL 1.8 V power VDD_24M_XTAL_1P8 1.71 1.8 1.89 V XTAL 1.8 V power VDD_DRAM_PLL_1P8 1.71 1.8 1.89 V Analog 1.8 V core power VDD_MIPI_0P9 0.855 0.9 1.000 V 0.9 V power for PLL and internal logic VDD_MIPI_1P2 1.14 1.2 1.26 V 1.2 V power for analog VDD_MIPI_1P8 VDD_PCI_0P86,7 VDD_PCI_1P86 1.71 0.805 1.71 1.8 0.850 1.800 1.89 0.900 1.890 V 1.8 V power for PLL and analog V Digital supply for PCIe PHY V 1.8 V supply for PCIe PHY VDD_USB_0P8 0.780 0.820 0.900 V Digital power supply from PHY’s I/O power pads VDD_USB_1P8 1.71 1.80 1.89 V 1.8 V analog power supply VDD_USB_3P3 3.069 3.30 3.6 V 3.3 V analog power supply USB1_VBUS USB2_VBUS 0.800 1.40 3.60 V USB_VBUS input detect signal Temperature Sensor — Accuracy8 �3 �5 �C Sensing temperature range 10�C to 105�C T J 0 — +95 oC See Table 2 for complete list of junction temperature capabilities. 1 The BD71847MWV PMIC does not support 0.950 V for VDD_GPU, VDD_VPU, and VDD_DRAM. For this PMIC, 0.975 V typical is acceptable and supported. 2 Applying the maximum voltage results in maximum power consumption and heat generation. A voltage set point = (Vmin + the supply tolerance) is recommended. This results in an optimized power/speed ratio. i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 18 NXP Semiconductors Electrical characteristics 3 Overdrive maximum voltage includes all the nominal frequencies. 4 50% duty cycle for 5 years 5 Booting VDD_SOC at 0.800 V �5% is acceptable (Vmin = 0.760 V). Software is expected to program the VDD_SOC voltage to the typical value in this table prior to first DRAM memory access. 6 Ensure the VDD_PCI_1P8 does not have more than 40 mVpp AC power supply noise superimposed on the high power supply voltage for the PHY core (1.8 V nominal DC value). Simultaneously, the VDD_PCI_0P8 should have no more than 20 mVpp AC power supply noise superimposed on the low power supply voltage for th PHY core (0.9 V nominal DC value for the overdrive). 7 It can be min 0.78 V when supplied but not operating PCIe. 8 “EN” of TMU Enable Register (TMU_TER) is required to be always enabled for the part to operate correctly. 3.1.4 External clock sources Each i.MX 8M Mini processor has two external input system clocks: a low frequency (RTC_XTALI) and a high frequency (XTALI). The RTC_XTALI is used for low-frequency functions. It supplies the clock for wake-up circuit, power-down real time clock operation, and slow system and watch-dog counters. The clock input can only be connected to an external oscillator. RTC_XTALO should be directly connected to VDD_SNVS_0P8. The system clock input XTALI is used to generate the main system clock. It supplies the PLLs and other peripherals. The system clock input can be connected to either an external oscillator or a crystal using internal oscillator amplifier. Table 11 shows the interface frequency requirements. Table 11. External input clock frequency Parameter Description Symbol Min Typ Max Unit RTC_XTALI Oscillator1 fckil — 32.7682 — XTALI Oscillator1,3 fxtal 24 1 The required frequency stability of this clock source is application dependent. 2 Recommended nominal frequency 32.768 kHz. 3 External oscillator or a fundamental frequency crystal appropriately coupled to the internal oscillator amplifier. kHz MHz The typical values shown in Table 11 are required for use with NXP software to ensure precise time keeping and USB operation. For RTC_XTALI operation, an external oscillator is necessary. RTC_XTALO should be directly connected to VDD_SNVS_0P8 when using an external 32.768 kHz oscillator. NOTE There is no internal RC oscillator. Table 12 shows the external input clock for OSC32K. Table 12. External input clock for OSC32K Symbol Min Frequency f — Typ 32.768 Max Unit — kHz i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 NXP Semiconductors 19 Electrical characteristics RTC_XTALI Symbol VIH VIL Table 12. External input clock for OSC32K Min Typ Max Unit 0.7 x NVCC_SNVS_1P8 — NVCC_SNVS_1P8 V 0 — 0.3 x NVCC_SNVS_1P8 V 3.1.5 Maximum supply currents Power consumption is highly dependent on the application. Estimating the maximum supply currents required for power supply design is difficult because the use cases that requires maximum supply current is not a realistic use cases. To help illustrate the effect of the application on power consumption, data was collected while running consumer standard benchmarks that are designed to be compute and graphic intensive. The results provided are intended to be used as guidelines for power supply design. VDD_ARM VDD_SOC VDD_GPU VDD_VPU VDD_DRAM VDD_ANA_0P8 VDD_ANA0_1P8 VDD_ANA1_1P8 NVCC_SNVS_1P8 VDD_ARM_PLL_1P8 VDD_24M_XTAL_1P8 PVCCx_1P8 NVCC_ NVCC_DRAM DRAM_VFEF Table 13. Maximum supply currents Power rail Max current Unit 2200 mA 1000 mA 500 mA 1000 mA 1000 mA 50 mA 250 mA 3 mA 100 mA 3 mA Imax = N x C x V x (0.5 x F) Where: N–Number of IO pins supplied by the power line C–Equivalent external capacitive load V–IO voltage (0.5 x F)–Data change rate. Up to 0.5 of the clock rate (F). In this equation, Imax is in Amps, C in Farads, V in Volts, and F in Hertz. 10 mA i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 20 NXP Semiconductors Electrical characteristics 3.1.6 Power modes The i.MX 8M Mini processors support the following power modes: � RUN Mode: All external power rails are on, CPU is active and running; other internal modules can be on/off based on application. � IDLE Mode: When there is no thread running and all high-speed devices are not active, the CPU can automatically enter this mode. The CPU can be in the power-gated state but with L2 data retained, DRAM and the bus clock are reduced. Most of the internal logic is clock gated but still remains powered. The M4 core can remain running. Compared with RUN mode, all the external power rails from the PMIC remain the same, and most of the modules still remain in their state. � SUSPEND Mode: The most efficient power saving mode where all the clocks are off and all the unnecessary power supplies are off. � SNVS Mode: This mode is also called RTC mode. Only the power for the SNVS domain remains on to keep RTC and SNVS logic alive. � OFF Mode: All power rails are off. Table 14. Chip power in different LP mode Mode Supply Typ.1 Unit SNVS VDD_SNVS_0P8 (0.8 V) 0.02 NVCC_SNVS_1P8 (1.8 V) 0.09 mW Total2 0.11 SUSPEND NVCC (1.8 V) 1.20 NVCC_DRAM (1.1 V) 0.50 NVCC_ENET (1.8 V) 0.10 NVCC_SNVS_1P8 (1.8 V) 0.10 PVCC (1.8 V) 0.60 mW VDD_MIPI_0P9 (0.9 V) 2.20 VDD_SNVS_0P8 (0.8 V) 0.10 VDD_SOC (0.82 V) 4.00 VDD_ARM_0P8 (0.82 V) 0.10 VDDA_PCIE_USB_0P8 (0.82 V) 3.00 Total2 11.90 1 All the power numbers defined in the table are for information only. These numbers are based on typical silicon at 25oC, under non-OS environment and use case dependent. For power numbers with OS and real use cases, see Power consumption measurement application note for more details. 2 Sum of the listed supply rails. i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 NXP Semiconductors 21 Electrical characteristics Table 15 summarizes the external power supply states in all the power modes. Power rail VDD_ARM VDD_SOC VDD_GPU VDD_VPU VDD_DRAM Misc_1P81 Misc_0P81 VDD_MIPI_1P2 VDD_MIPI_0P9 VDD_DRAM_PLL_0P8 VDD_SNVS_0P8 NVCC_SNVS_1P8 NVCC_ PVCCx_1P8 NVCC_DRAM 1 See Table 16 Table 15. The power supply states OFF SNVS SUSPEND OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF ON ON OFF OFF OFF OFF ON OFF OFF OFF ON ON OFF OFF ON ON ON ON ON ON IDLE ON ON OFF OFF ON ON ON ON ON ON ON ON ON ON ON RUN ON ON ON/OFF ON/OFF ON ON ON ON ON ON ON ON ON ON ON Misc_1P8 Misc_0P8 Table 16. Group name VDD_24M_XTAL_1P8 VDD_ANA0_1P8 VDD_ANA1_1P8 VDD_ARM_PLL_1P8 VDD_DRAM_PLL_1P8 VDD_MIPI_1P8 VDD_PCI_1P8 VDD_USB_1P8 VDD_ANA_0P8 VDD_ARM_PLL_0P8 VDD_PCI_0P8 VDD_USB_0P8 i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 22 NXP Semiconductors Electrical characteristics 3.2 Power supplies requirements and restrictions The system design must comply with power-up sequence, power-down sequence, and steady state guidelines as described in this section to guarantee the reliable operation of the device. Any deviation from these sequences may result in the following situations: � Excessive current during power-up phase � Prevention of the device from booting � Irreversible damage to the processor (worst-case scenario) 3.2.1 Power-up sequence Figure 5 illustrates the power-up sequence of i.MX 8M Mini processor. NVCC_SNVS_1P8 VDD_SNVS_0P8 RTC_RESET_B 32K RTC_XTALI PMIC_ON_REQ VDD_SOC,VDD_ANA_0P8,VDD_ARM_PLL_0P8 VDD_PCI_0P8,VDD_USB_0P8 VDD_GPU,VDD_VPU,VDD_DRAM, VDD_DRAM_PLL_0P8 VDD_MIPI_0P9 VDD_ARM VDD_ANAx_1P8,VDD_DRAM_PLL_1P8,VDD_MIPI_1P8, VDD_24M_XTAL_1P8,VDD_USB_1P8,VDD_PCI_1P8 VDD_ARM_PLL_1P8 PVCCx_1P8, NVCC_xxx (1.8 V) NVCC_DRAM NVCC_xxx (2.5 and 3.3 V),VDD_USB_3P3 VDD_MIPI_1P2 POR_B T1 T2 T3 t1 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 Figure 3. The power-up sequence i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 NXP Semiconductors 23 Electrical characteristics Table 17 represents the timing parameters of the power-up sequence. Table 17. Power-up sequence Description Min Typ Max Unit T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T131 Delay from NVCC_SNVS_1P8 to VDD_SNVS_0P8 Delay from VDD_SNVS_0P8 high or RTC_SET_B de-assert Delay from RTC_RESET_B de-assert to stable 32 k existed Delay from PMIC_ON_REQ assert to analog 0.8 V on Delay from analog 0.8 V on to analog 0.8/0/9 V on Delay from analog 0.8/0.9 V on to PHY 0.9 V on Delay from PHY 0.9 V on to VDD_ARM on Delay from VDD_ARM on to analog 1.8 V on Delay from analog 1.8 V on to digital 1.8 V on Delay from digital 1.8 V on to NVCC_DRAM on Delay from NVCC_DRAM on to digital 2.5 V and 3.3 V on Delay from digital 2.5 V and 3.3 V on to PHY 1.2 V on Delay from PHY 1.2 V on to POR_B de-assert 0 2 — ms 0 10 — ms — 40 100 s 0 0.2 — ms 0 2 — ms 0 15 — s 0 2 — ms 0 15 — s 0 2 — ms 0 2 — ms 0 2 — ms 0 2 — ms 0 20 — ms t1 Uncertain period before PMIC_ON_REQ assert during VDD_SNVS_0P8 ramp up. For ramp up requirement, only VDD_ANA0_1P8 has 5 s minimum requirement, others do not have such requirement. During power-up, make sure NVCC_xxx – PVCCx_1P8 < 2 V. 1 The values of T13 depend on T2. RTC_RESET_B must be de-assert before POR_B de-asserts. 3.2.2 Power-down sequence Figure 5 illustrates the power-down sequence of i.MX 8M Mini processor. i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 24 NXP Semiconductors Electrical characteristics VDD_MIPI_1P2 NVCC_xxx (2.5 and 3.3 V) NVCC_DRAM PVCCx_1P8, NVCC_xxx (1.8V) VDD_ANAx_1P8, VDD_DRAM_PLL_1P8,VDD_MIPI_1P8 VDD_24M_XTAL_1P8,VDD_USB_1P8,VCC_PCI_1P8 VDD_ARM VDD_MIPI_0P9 VDD_GPU, VDD_VPU, VDD_DRAM VDD_DRAM_PLL_0P8 VDD_SOC, VDD_ANA_0P8 VDD_PCI_0P8, VDD_USB_0P8 32K RTC_XTALI RTC_RESET_B VDD_SNVS_0P8 NVCC_SNVS_1P8 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 Figure 4. The power-down sequence i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 NXP Semiconductors 25 Electrical characteristics Table 18 represents the timing parameters of the power-down sequence. Table 18. Power-down sequence Description Min T1 Delay from PHY 1.2 V off to digital 2.5 V and 3.3 V off 0 T2 Delay from digital 2.5 V and 3.3 V off to NVCC_DRAM off 0 T3 Delay from NVCC_DRAM off to digital 1.8 V off 0 T4 Delay from digital 1.8 V off to analog 1.8 V off 0 T5 Delay from analog 1.8 V off to VDD_ARM off 0 T6 Delay from VDD_ARM off to PHY 0.9 V off 0 T7 Delay from PHY 0.9 V off to analog 0.8/0.9 V off 0 T8 Delay from analog 0.8/0.9 V off to analog 0.8 V off 0 T9 Delay from analog 0.8 V off to 32k off 0 T10 Delay from 32k off to RTC_RESET_B assert 0 T11 Delay from RTC_RESET_B assert to VDD_SNVS_0P8 off 0 T12 Delay from VDD_SNVS_0P8 off to NVCC_SNVS_1P8 off 0 During power-down, make sure NVCC_xxx - PVCCx_1P8 < 2 V. 3.3 PLL electrical characteristics Table 19 shows PLL electrical characteristics. PLL type AUDIO_PLL1 AUDIO_PLL2 VIDEO_PLL1 SYS_PLL1 Table 19. PLL electrical parameters Parameter Clock output range Reference clock Lock time Clock output range Reference clock Lock time Clock output range Reference clock Lock time Clock output range Reference clock Lock time Typ Max Unit 10 -- ms 10 -- ms 10 -- ms 10 -- ms 10 -- ms 10 -- ms 10 -- ms 10 -- ms 10 -- ms 10 -- ms 10 -- ms 10 -- ms Value Maximum 650 MHz 24 MHz 375 s Maximum 650 MHz 24 MHz 375 s Maximum 650 MHz 24 MHz 375 s 800 MHz 24 MHz 25 s i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 26 NXP Semiconductors PLL type SYS_PLL2 SYS_PLL3 ARM_PLL DRAM_PLL GPU_PLL VPU_PLL Electrical characteristics Table 19. PLL electrical parameters (continued) Parameter Value Clock output range Reference clock Lock time Clock output range Reference clock Lock time Clock output range Reference clock Lock time Clock output range Reference clock Lock time Clock output range Reference clock Lock time Clock output range Reference clock Lock time 1 GHz 24 MHz 25 s 600 MHz ~ 1 GHz 24 MHz 25 s 800 MHz ~1.6 GHz 24 MHz 25 s Maximum 750 MHz 24 MHz 375 s Maximum 1 GHz 24 MHz 25 s 400 MHz ~ 800 MHz 24 MHz 25 s 3.4 On-chip oscillators 3.4.1 OSC24M A 24 MHz oscillator is used as the primary clock source for the PLLs to generate the clock for the CPU, BUS, and high-speed interfaces. For fractional PLLs, the 24 MHz clock from the oscillator can be used as the PLL reference clock directly. Parameter Description Frequency Cload Drive level ESR Table 20. Crystal specifications1 Min Typ -- 24 -- 12 100 -- -- -- Max Unit -- MHz -- pF -- W 80 i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 NXP Semiconductors 27 Electrical characteristics 1 Actual working drive level is depend on real design. Please contact crystal vendor for selecting drive level of crystal. 3.4.2 OSC32K An external 32.768 kHz oscillator is necessary. 3.5 General purpose I/O (GPIO) DC parameters Table 21 shows DC parameters for GPIO pads. The parameters in Table 21 are guaranteed per the operating ranges in Table 10, unless otherwise noted. Table 21. GPIO DC parameters Parameter Symbol Test Conditions Min Typ Max Unit High-level output voltage VOH (1.8 V) IOH = 1.6/3.2/6.4/9.6 mA (1.8 V) 0.8 x VDD -- VOH (3.3 V) IOH = 2/4/8/12 mA (3.3 V) 0.8 x VDD -- VDD V VDD V Low-level output voltage VOL (1.8 V) IOL = 1.6/3.2/6.4/9.6 mA (1.8 V) 0 VOL (3.3 V) IOL = 2/4/8/12 mA (3.3 V) 0 -- 0.2 x VDD V -- 0.2 x VDD V High-level input voltage VIH -- 0.7 x VDD -- VDD + 0.3 V Low-level input voltage VIL -- -0.3 -- 0.3 x VDD V Pull-up resistor -- Pull-down resistor -- VDD = 1.65 - 1.95V Temp = 0 - 95 oC 12 22 49 K 13 23 48 K Pull-up resistor -- Pull-down resistor -- VDD = 2.25 - 2.75V Temp = 0 - 95 oC Pull-up resistor1 -- Pull-down resistor1 -- VDD = 3.0 - 3.6V Temp = 0 - 95 oC High level input current IIH -- Low level input current IIL -- 1 Does not support internal pull-up or pull-down for 3.3 V IOs. 13 24 9.1 33 -- -- -- -- -4 -- -0.7 -- 69 K 69 K -- K -- K 4 A 0.7 A Parameter High level input current Table 22. Additional leakage parameters Symbol Pins Min PCIE_RXN, USBx_Dx -30 IIH PCIE_CLK -8 MIPI_CSI -4 Max Unit 30 8 A 4 i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 28 NXP Semiconductors Parameter Low level input current Electrical characteristics Table 22. Additional leakage parameters (continued) Symbol IIL Pins JTAG_TRST_B, USBx_ID PCIE_CLK, USBx_Dx PCIE_RXN MIPI_CSI, ONOFF, POR_B Min -200 -6 -2.5 -0.7 Max Unit 200 6 A 2.5 0.7 3.5.1 DDR I/O DC electrical characteristics The DDR I/O pads support LPDDR 4, DDR4, and DDR3L operational modes. The DDR Memory Controller (DDRMC) is designed to be compatible with JEDEC-compliant SDRAMs. DDRMC operation is contingent upon the board's DDR design adherence to the DDR design and layout requirements stated in the hardware development guide for the i.MX 8M Mini applications processor. 3.6 I/O AC parameters This section includes the AC parameters of the following I/O types: � General Purpose I/O (GPIO) The GPIO load circuit and output transition time waveforms are shown in Figure 5 and Figure 6. FUronmdeOr uTtepsutt Test Point CL CL includes package, probe and fixture capacitance Figure 5. Load circuit for output 80% Output (at pad) 20% tr tf Figure 6. Output transition time waveform 3.6.1 General purpose I/O AC parameters This section presents the I/O AC parameters for GPIO in different modes. OVDD 80% 20%0 V i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 NXP Semiconductors 29 Electrical characteristics Table 23. Maximum frequency of operation for input Maximum frequency (MHz) VDD = 1.8 V, CL = 50 pF VDD = 3.3 V, CL = 50 pF 450 440 dse[2:0] 00X 00X 10X 10X 01X 01X 11X 11X Table 24. Maximum frequency of operation for output Parameter Maximum Frequency (MHz) VDD = 1.8 V VDD = 3.3 V sre[1:0] Driver type CL = 10 pF CL = 20 pF CL = 10 pF CL = 20 pF 0X 1x Slow Slew 150 80 120 65 1X 1x Fast Slew 150 80 120 65 0X 2x Slow Slew 160 90 150 80 1X 2x Fast Slew 160 90 150 80 0X 4x Slow Slew 200 100 180 90 1X 4x Fast Slew 200 100 180 90 0X 6x Slow Slew 250 130 200 100 1X 6x Fast Slew 250 130 200 100 3.7 Output buffer impedance parameters This section defines the I/O impedance parameters of the i.MX 8M Mini family of processors for the following I/O types: NOTE DDR I/O output driver impedance is measured with "long" transmission line of impedance Ztl attached to I/O pad and incident wave launched into transmission line. Rpu/Rpd and Ztl form a voltage divider that defines specific voltage of incident wave relative to OVDD. Output driver impedance is calculated from this voltage divider (see Figure 7). i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 30 NXP Semiconductors ipp_do predriver U,(V) VDD OVDD PMOS (Rpu) pad NMOS (Rpd) OVSS Electrical characteristics Ztl W, L = 20 inches Cload = 1p Vin (do) 0 U,(V) OVDD Vref Vref1 Vref2 t,(ns) Vout (pad) 0 Vovdd - Vref1 Rpu = x Ztl Vref1 Vref2 Rpd = x Ztl Vovdd - Vref2 Figure 7. Impedance matching load for measurement t,(ns) i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 NXP Semiconductors 31 Electrical characteristics 3.7.1 DDR I/O output buffer impedance Table 25 shows DDR I/O output buffer impedance of i.MX 8M Mini family of processors. Table 25. DDR I/O output buffer impedance Parameter Symbol Test Conditions DSE (Drive Strength) Typical NVCC_DRAM = 1.35 NVCC_DRAM = 1.2 NVCC_DRAM = 1.1 V (DDR3L) V (DDR4) V (LPDDR4) Unit Output Driver Impedance Rdrv 000000 000010 001000 001010 011000 011010 111000 111010 Hi-Z Hi-Z Hi-Z 240 240 240 120 120 120 80 80 80 60 60 60 48 48 48 40 40 40 34 34 34 Note: 1. Output driver impedance is controlled across PVTs using ZQ calibration procedure. 2. Calibration is done against 240 external reference resistor. 3. Output driver impedance deviation (calibration accuracy) is �5% (max/min impedance) across PVTs. 3.8 System modules timing This section contains the timing and electrical parameters for the modules in each i.MX 8M Mini processor. 3.8.1 Reset timings parameters Figure 8 shows the reset timing and Table 26 lists the timing parameters. POR_B (Input) CC1 Figure 8. Reset timing diagram Table 26. Reset timing parameters ID Parameter Min Max CC1 Duration of POR_B to be qualified as valid. 1-- Unit RTC_XTALI cycle i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 32 NXP Semiconductors Electrical characteristics 3.8.2 WDOG Reset timing parameters Figure 9 shows the WDOG reset timing and Table 27 lists the timing parameters. WDOGx_B (Output) CC3 Figure 9. WDOGx_B timing diagram Table 27. WDOGx_B timing parameters ID CC3 Parameter Duration of WDOGx_B Assertion Min Max 1-- Unit RTC_XTALI cycle NOTE RTC_XTALI is approximately 32 kHz. RTC_XTALI cycle is one period or approximately 30 s. NOTE WDOGx_B output signals (for each one of the Watchdog modules) do not have dedicated pins, but are muxed out through the IOMUX. See the IOMUXC chapter of the i.MX 8M Mini Applications Processor Reference Manual (IMX8MMRM) for detailed information. 3.9 External peripheral interface parameters The following subsections provide information on external peripheral interfaces. 3.9.1 ECSPI timing parameters This section describes the timing parameters of the ECSPI blocks. The ECSPI have separate timing parameters for master and slave modes. i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 NXP Semiconductors 33 Electrical characteristics 3.9.1.1 ECSPI Master mode timing Figure 10 depicts the timing of ECSPI in master mode. Table 28 lists the ECSPI master mode timing characteristics. ECSPIx_RDY_B ECSPIx_SS_B ECSPIx_SCLK ECSPIx_MOSI ECSPIx_MISO CS10 CS8 CS1 CS3 CS7 CS3 CS9 CS2 CS2 CS6 CS5 CS4 Figure 10. ECSPI Master mode timing diagram Table 28. ECSPI Master mode timing parameters ID Parameter Symbol Min Max Unit CS1 ECSPIx_SCLK Cycle Time�Read ECSPIx_SCLK Cycle Time�Write tclk 43 -- ns 15 CS2 ECSPIx_SCLK High or Low Time�Read ECSPIx_SCLK High or Low Time�Write tSW 21.5 -- ns 7 CS3 ECSPIx_SCLK Rise or Fall1 tRISE/FALL -- -- ns CS4 ECSPIx_SS_B pulse width tCSLH Half ECSPIx_SCLK period -- ns CS5 ECSPIx_SS_B Lead Time (CS setup time) tSCS Half ECSPIx_SCLK period - 4 -- ns CS6 ECSPIx_SS_B Lag Time (CS hold time) tHCS Half ECSPIx_SCLK period - 2 -- ns CS7 ECSPIx_MOSI Propagation Delay (CLOAD = 20 pF) tPDmosi -1 1 ns CS8 ECSPIx_MISO Setup Time tSmiso 18 -- ns CS9 ECSPIx_MISO Hold Time tHmiso 0 CS10 RDY to ECSPIx_SS_B Time2 tSDRY 5 1 See specific I/O AC parameters Section 3.6, I/O AC parameters." 2 SPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals. -- ns -- ns i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 34 NXP Semiconductors Electrical characteristics 3.9.1.2 ECSPI Slave mode timing Figure 11 depicts the timing of ECSPI in Slave mode. Table 29 lists the ECSPI Slave mode timing characteristics. ECSPIx_SS_B ECSPIx_SCLK ECSPIx_MISO CS7 ECSPIx_MOSI CS1 CS9 CS8 CS2 CS2 CS6 CS5 CS4 Figure 11. ECSPI Slave mode timing diagram Table 29. ECSPI Slave mode timing parameters ID Parameter CS1 ECSPIx_SCLK Cycle Time�Read ECSPI_SCLK Cycle Time�Write CS2 ECSPIx_SCLK High or Low Time�Read ECSPIx_SCLK High or Low Time�Write CS4 ECSPIx_SS_B pulse width CS5 ECSPIx_SS_B Lead Time (CS setup time) CS6 ECSPIx_SS_B Lag Time (CS hold time) CS7 ECSPIx_MOSI Setup Time CS8 ECSPIx_MOSI Hold Time CS9 ECSPIx_MISO Propagation Delay (CLOAD = 20 pF) Symbol tclk tSW tCSLH tSCS tHCS tSmosi tHmosi tPDmiso Min 15 43 7 21.5 Half ECSPIx_SCLK period 5 5 4 4 4 Max Unit -- ns -- ns -- ns -- ns -- ns -- ns -- ns 19 ns i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 NXP Semiconductors 35 Electrical characteristics 3.9.2 Ultra-high-speed SD/SDIO/MMC host interface (uSDHC) AC timing This section describes the electrical information of the uSDHC, which includes SD/eMMC 5.1 (single data rate) timing, eMMC 5.1/SD3.0 (dual data rate) AC timing, and SDR50/SDR104 AC timing. 3.9.2.1 SD3.0/eMMC 5.1 (single data rate) AC timing Figure 12 depicts the timing of SD3.0/eMMC5.1 (SDR), and Table 30 lists the SD3.0/eMMC5.1 (SDR) timing characteristics. SD4 SD2 SD1 SD5 SDx_CLK SD3 SD6 Output from uSDHC to card SDx_DATA[7:0] SD7 SD8 Input from card to uSDHC SDx_DATA[7:0] Figure 12. SD3.0/eMMC5.1 (SDR) timing Table 30. SD3.0/eMMC5.1 (SDR) interface timing specification ID Parameter Symbols Min Card Input Clock SD1 SD2 SD3 SD4 SD5 Clock Frequency (Low Speed) Clock Frequency (SD/SDIO Full Speed/High Speed) Clock Frequency (MMC Full Speed/High Speed) fPP1 0 fPP2 0 fPP3 0 Clock Frequency (Identification Mode) fOD 100 Clock Low Time tWL 7 Clock High Time tWH 7 Clock Rise Time tTLH -- Clock Fall Time tTHL -- uSDHC Output/Card Inputs SD_CMD, SDx_DATAx (Reference to CLK) SD6 uSDHC Output Delay tOD 6.6 Max 400 25/50 20/52 400 -- -- 3 3 3.6 Unit kHz MHz MHz kHz ns ns ns ns ns i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 36 NXP Semiconductors Electrical characteristics Table 30. SD3.0/eMMC5.1 (SDR) interface timing specification (continued) ID Parameter Symbols Min Max Unit uSDHC Input/Card Outputs SD_CMD, SDx_DATAx (Reference to CLK) SD7 uSDHC Input Setup Time tISU 2.5 -- ns SD8 uSDHC Input Hold Time4 tIH 1.5 -- ns 1 In Low-Speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V. 2 In Normal (Full) -Speed mode for SD/SDIO card, clock frequency can be any value between 0�25 MHz. In High-speed mode, clock frequency can be any value between 0�50 MHz. 3 In Normal (Full) -Speed mode for MMC card, clock frequency can be any value between 0�20 MHz. In High-speed mode, clock frequency can be any value between 0�52 MHz. 4 To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns. 3.9.2.2 eMMC 5.1/SD3.0 (dual data rate) AC timing Figure 13 depicts the timing of eMMC 5.1/SD3.0 (DDR). Table 31 lists the eMMC 5.1/SD3.0 (DDR) timing characteristics. Be aware that only DATA is sampled on both edges of the clock (not applicable to CMD). SD1 SDx_CLK SD2 SD2 Output from eSDHCv3 to card SDx_DATA[7:0] SD3 SD4 Input from card to eSDHCv3 SDx_DATA[7:0] ...... ...... Figure 13. eMMC5.1/SD3.0 (DDR) timing Table 31. eMMC5.1/SD3.0 (DDR) interface timing specification ID Parameter Symbols Min Max Card Input Clock SD1 Clock Frequency (eMMC5.1 DDR) SD1 Clock Frequency (SD3.0 DDR) fPP 0 52 fPP 0 50 uSDHC Output / Card Inputs SD_CMD, SDx_DATAx (Reference to CLK) SD2 uSDHC Output Delay tOD 2.7 6.9 uSDHC Input / Card Outputs SD_CMD, SDx_DATAx (Reference to CLK) Unit MHz MHz ns i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 NXP Semiconductors 37 Electrical characteristics Table 31. eMMC5.1/SD3.0 (DDR) interface timing specification (continued) ID Parameter Symbols Min Max Unit SD3 uSDHC Input Setup Time SD4 uSDHC Input Hold Time tISU 2.4 -- ns tIH 1.3 -- ns 3.9.2.3 HS400 DDR AC timing Figure 14 depicts the timing of HS400 mode, and Table 32 lists the HS400 timing characteristics. Be aware that only data is sampled on both edges of the clock (not applicable to CMD). The CMD input/output timing for HS400 mode is the same as CMD input/output timing for SDR104 mode. Check SD5, SD6, and SD7 parameters in Table 34 SDR50/SDR104 Interface Timing Specification for CMD input/output timing for HS400 mode. SCK DAT0 Output from uSDHC to eMMC D.A..T1 DAT7 Strobe DAT0 Input from eMMC to uSDHC D.A..T1 DAT7 SD1 SD2 SD3 SD4 SD5 SD4 SD5 SD6 SD7 Figure 14. HS400 timing Table 32. HS400 interface timing specification ID Parameter Symbols Min SD1 SD2 SD3 SD4 SD5 Card Input Clock Clock frequency Clock low time Clock high time fPP 0 tCL 0.46 x tCLK tCH 0.46 x tCLK uSDHC Output/Card Inputs DAT (Reference to SCK) Output skew from data of edge of SCK tOSkew1 0.45 Output skew from edge of SCk to data tOSkew2 0.45 uSDHC Input/Card Outputs DAT (Reference to Strobe) Max 200 0.54 x tCLK 0.54 x tCLK -- -- Unit MHz ns ns ns ns i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 38 NXP Semiconductors Electrical characteristics Table 32. HS400 interface timing specification (continued) ID Parameter SD6 uSDHC input skew SD7 uSDHC hold skew Symbols Min tRQ -- tRQH -- Max Unit 0.45 ns 0.45 ns 3.9.2.4 HS200 Mode AC timing Figure 15 depicts the timing of HS200 mode, and Table 33 lists the HS200 timing characteristics. SCK 8-bit output from uSDHC to eMMC SD1 SD2 SD3 SD4/SD5 8-bit input from eMMC to uSDHC SD8 Figure 15. HS200 timing iti Table 33. HS200 interface timing specification ID Parameter Symbols Min Max Unit Card Input Clock SD1 Clock Frequency Period tCLK 5.0 -- ns SD2 Clock Low Time tCL 0.3 x tCLK 0.7 x tCLK ns SD3 Clock High Time tCH 0.3 x tCLK 0.7 x tCLK ns uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK) SD5 uSDHC Output Delay tOD -1.6 1 ns uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)1 SD8 uSDHC Output Data Window 1 HS200 is for 8 bits while SDR104 is for 4 bits. tODW 0.5 x tCLK -- ns i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 NXP Semiconductors 39 Electrical characteristics 3.9.2.5 SDR50/SDR104 AC timing Figure 16 depicts the timing of SDR50/SDR104, and Table 34 lists the SDR50/SDR104 timing characteristics. SCK SD1 SD2 SD3 SD4/SD5 8-bit output from uSDHC to eMMC 8-bit input from eMMC to uSDHC SD6 SD7 SD8 Figure 16. SDR50/SDR104 timing Table 34. SDR50/SDR104 interface timing specification ID Parameter Symbols Min Max Unit Card Input Clock SD1 Clock Frequency Period tCLK 5 -- ns SD2 Clock Low Time tCL 0.46 x tCLK 0.54 x tCLK ns SD3 Clock High Time tCH 0.46 x tCLK 0.54 x tCLK ns uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR50 (Reference to CLK) SD4 uSDHC Output Delay tOD -3 1 ns uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR104 (Reference to CLK) SD5 uSDHC Output Delay tOD -1.6 1 ns uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR50 (Reference to CLK) SD6 uSDHC Input Setup Time tISU 2.4 -- ns SD7 uSDHC Input Hold Time tIH 1.4 -- ns uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR104 (Reference to CLK)1 SD8 uSDHC Output Data Window 1 Data window in SDR100 mode is variable. tODW 0.5 x tCLK -- ns 3.9.2.6 Bus operation condition for 3.3 V and 1.8 V signaling Signaling level of SD/eMMC4.5/5.0/5.1 can be 1.8 V or 3.3 V depending on the working mode. The DC parameters for the NVCC_SD1, NVCC_SD2 and NVCC_SD3 supplies are identical to those shown in Table 21, "GPIO DC parameters," on page 28. i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 40 NXP Semiconductors Electrical characteristics 3.9.3 Ethernet controller (ENET) AC electrical specifications The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface. Table 35. ENET signal mapping Pad name Description Mode Alt mode Direction Comments ENET_MDC enet1.MDC RMII/RGMII ALT0 O -- ENET_MDIO enet1.MDIO RMII/RGMII ALT0 I/O -- ENET_TD3 RGMII.TD3 RGMII ALT0 O Only used for RGMII ENET_TD2 RMII.CLK; RGMII.TD2 RMII/RGMII ALT0 I/O Used as RMII clock and RGMII data, there are two RGMII clock schemes. � MAC generate output 50M reference clock for PHY, and MAC also use this 50M clock. � MAC use external 50M clock. ENET_TD1 RMII and RGMII.TD1 RMII/RGMII ALT0 O -- ENET_TD0 RMII and RGMII.TD0 RMII/RGMII ALT0 O -- ENET_TX_CTL RMII.TX_EN; RMII/RGMII RGMII.TX_CTL ALT0 O -- ENET_TXC RMII.TX_ERR; RGMII ALT0/ALT1 O For RMII--ENET_TXC works as RGMII. TX_CLK RMII.TX_ERR need to work in the ALT1 mode. For RGMII--ENET_TXC works as RGMII.TX_CLK need to work in the ALT0 mode. ENET_RX_CTL RMII.RX_EN (CRS_DV); RGMII.RC_CTL RMII/RGMII ALT0 I -- ENET_RXC RMII.RX_ERR; RGMII ALT0/ALT1 I For RMII--ENET_RXC works as RGMII.RX_CLK RMII.RX_ERR need to work in the ALT1 mode. For RGMII--ENET_RXC works as RGMII.RX_CLK need to work in the ALT0 mode. ENET_RD0 RMII and RGMII.RD0 RMII/RGMII ALT0 I -- ENET_RD1 RMII and RGMII.RD1 RMII/RGMII ALT0 I -- ENET_RD2 RGMII.RD2 RGMII ALT0 I -- ENET_RD3 RGMII.RD3 RGMII ALT0 I -- GPIO1_IO06 enet1.MDC RMII/RGMII ALT1 O -- GPIO1_IO07 enet1.MDIO RMII/RGMII ALT1 I/O -- I2C1_SCL enet1.MDC RMII/RGMII ALT1 O -- i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 NXP Semiconductors 41 Electrical characteristics Table 35. ENET signal mapping (continued) Pad name Description Mode Alt mode Direction Comments I2C1_SDA I2C2_SCL I2C2_SDA GPIO1_IO00 GPIO1_IO08 enet1.MDIO enet1.1588_EV ENT1_IN enet1.1588_EV ENT1_OUT ENET_PHY_RE F_CLK_ROOT enet1.1588_EV ENT0_IN RMII/RGMII RMII/RGMII RMII/RGMII RGMII RMII/RGMII ALT1 ALT1 ALT1 ALT1 ALT1 GPIO1_IO09 enet1.1588_EV RMII/RGMII ENT0_OUT ALT1 I/O -- O -- I/O -- O Reference clock for PHY. I Capture/compare block input/output event bus signal. When configured for capture and a rising edge is detected, the current timer value is latched and transferred into the corresponding ENET_TCCRn register for inspection by software. When configured for compare, the corresponding signal 1588_EVENT is asserted for one cycle when the timer reaches the compare value programmed in register ENET_TCCRn. An interrupt or DMA request can be triggered if the corresponding bit in ENET_TCSRn[TIE] or ENET_TSCRn[TDRE] is set. O -- 3.9.3.1 RMII mode timing Figure 17 shows RMII mode timings. Table 36 describes the timing parameters (M16�M21) shown in the figure. i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 42 NXP Semiconductors Electrical characteristics ENET_CLK (input) M16 M17 M18 ENET_TX_DATA (output) ENET_TX_EN ENET_RX_EN (input) ENET_RX_DATA[1:0] ENET_RX_ER M19 M20 M21 Figure 17. RMII mode signal timing diagram Table 36. RMII signal timing ID Characteristic Min. M16 ENET_CLK pulse width high 35% M17 ENET_CLK pulse width low 35% M18 ENET_CLK to ENET0_TXD[1:0], ENET_TX_DATA invalid 4 M19 ENET_CLK to ENET0_TXD[1:0], ENET_TX_DATA valid -- M20 ENET_RX_DATAD[1:0], ENET_RX_EN(ENET_RX_EN), ENET_RX_ER to 4 ENET_CLK setup M21 ENET_CLK to ENET_RX_DATAD[1:0], ENET_RX_EN, ENET_RX_ER hold 2 Max. Unit 65% 65% -- 15 -- ENET_CLK period ENET_CLK period ns ns ns -- ns 3.9.3.2 RGMII signal switching specifications The following timing specifications meet the requirements for RGMII interfaces for a range of transceiver devices. Table 37. RGMII signal switching specifications1 Symbol Tcyc2 TskewT3 TskewR3 Duty_G4 Duty_T4 Tr/Tf Description Clock cycle duration Data to clock output skew at transmitter Data to clock input skew at receiver Duty cycle for Gigabit Duty cycle for 10/100T Rise/fall time (20�80%) Min. 7.2 -500 1 45 40 -- Max. Unit 8.8 ns 500 ps 2.6 ns 55 % 60 % 0.75 ns i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 NXP Semiconductors 43 Electrical characteristics 1 The timings assume the following configuration: DDR_SEL = (11)b DSE (drive-strength) = (111)b 2 For 10 Mbps and 100 Mbps, Tcyc will scale to 400 ns �40 ns and 40 ns �4 ns respectively. 3 For all versions of RGMII prior to 2.0; this implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns and less than 2.0 ns will be added to the associated clock signal. For 10/100, the Max value is unspecified. 4 Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domain as long as minimum duty cycle is not violated and stretching occurs for no more than three Tcyc of the lowest speed transitioned between. 2'-))?48#ATTRANSMITTER 2'-))?48$NNTO 4SKEW4 2'-))?48?#4, 48%. 48%22 4SKEW2 2'-))?48#ATRECEIVER Figure 18. RGMII transmit signal timing diagram original 2'-))?28#ATTRANSMITTER 2'-))?28$NNTO 4SKEW4 2'-))?28?#4, 28$6 28%22 4SKEW2 2'-))?28#ATRECEIVER Figure 19. RGMII receive signal timing diagram original i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 44 NXP Semiconductors Electrical characteristics 2'-))?28#SOURCEOFDATA )NTERNALDELAY 2'-))?28$NNTO 4SETUP4 4HOLD4 2'-))?28?#4, 2'-))?28#ATRECEIVER 28$6 28%22 4SETUP2 4HOLD2 Figure 20. RGMII receive signal timing diagram with internal delay 3.9.4 General-purpose media interface (GPMI) timing The i.MX 8M Mini GPMI controller is a flexible interface NAND Flash controller with 8-bit data width, up to 200 MB/s I/O speed and individual chip select. It supports Asynchronous Timing mode, Source Synchronous Timing mode and Toggle Timing mode separately, as described in the following subsections. 3.9.4.1 Asynchronous mode AC timing (ONFI 1.0 compatible) Asynchronous mode AC timings are provided as multiplications of the clock cycle and fixed delay. The maximum I/O speed of GPMI in Asynchronous mode is about 50 MB/s. Figure 21 through Figure 24 depicts the relative timing between GPMI signals at the module level for different operations under Asynchronous mode. Table 38 describes the timing parameters (NF1�NF17) that are shown in the figures. .!.$?#,% .!.$?#%?" .!.$?7%?" .!.$?!,% .!.$?$!4!XX NF1 NF3 NF2 NF4 NF5 NF6 NF7 NF8 NF9 Command Figure 21. Command Latch cycle timing diagram i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 NXP Semiconductors 45 Electrical characteristics .!.$?#,% .!.$?#%?" .!.$?7%?" NF1 NF3 NF10 NF5 NF11 .!.$?!,% NAND_DATAxx NF6 NF8 Address NF7 NF9 Figure 22. Address Latch cycle timing diagram .!.$?#,% .!.$?#%?" .!.$?7%?" NF1 NF3 NF10 NF5 NF11 .!.$?!,% NF6 NF7 .!.$?$!4!XX NF8 NF9 Data to NF Figure 23. Write Data Latch cycle timing diagram .!.$?#,% .!.$?#%?" .!.$?2%?" NF14 NF13 NF15 .!.$?2%!$9?" NF12 NF16 NF17 .!.$?$!4!XX Data from NF Figure 24. Read Data Latch cycle timing diagram (Non-EDO Mode) .!.$?#,% .!.$?#%?" .!.$?2%?" NF14 NF13 NF15 .!.$?2%!$9?" NF12 NAND_DATAxx NF16 NF17 Data from NF Figure 25. Read Data Latch cycle timing diagram (EDO mode) i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 46 NXP Semiconductors Electrical characteristics Table 38. Asynchronous mode timing parameters1 Timing ID Parameter Symbol T = GPMI Clock Cycle Unit Min. Max. NF1 NAND_CLE setup time tCLS (AS + DS) T - 0.12 [see notes2,3] ns NF2 NAND_CLE hold time tCLH DH T - 0.72 [see note2] ns NF3 NAND_CE0_B setup time tCS (AS + DS + 1) T [see notes3,2] ns NF4 NAND_CE0_B hold time tCH (DH+1) T - 1 [see note2] ns NF5 NAND_WE_B pulse width tWP DS T [see note2] ns NF6 NAND_ALE setup time tALS (AS + DS) T - 0.49 [see notes3,2] ns NF7 NAND_ALE hold time tALH DH T - 0.42 [see note2] ns NF8 Data setup time tDS DS T - 0.26 [see note2] ns NF9 Data hold time tDH DH T - 1.37 [see note2] ns NF10 Write cycle time tWC (DS + DH) T [see note2] ns NF11 NAND_WE_B hold time tWH DH T [see note2] ns NF12 Ready to NAND_RE_B low tRR4 (AS + 2) T [see 3,2] -- ns NF13 NAND_RE_B pulse width tRP DS T [see note2] ns NF14 READ cycle time tRC (DS + DH) T [see note2] ns NF15 NAND_RE_B high hold time tREH DH T [see note2] ns NF16 Data setup on read tDSR -- (DS T -0.67)/18.38 [see ns notes5,6] NF17 Data hold on read tDHR 0.82/11.83 [see notes5,6] -- ns 1 GPMI's Asynchronous mode output timing can be controlled by the module's internal registers HW_GPMI_TIMING0_ADDRESS_SETUP, HW_GPMI_TIMING0_DATA_SETUP, and HW_GPMI_TIMING0_DATA_HOLD. This AC timing depends on these registers settings. In the table, AS/DS/DH represents each of these settings. 2 AS minimum value can be 0, while DS/DH minimum value is 1. 3 T = GPMI clock period -0.075 ns (half of maximum p-p jitter). 4 NF12 is guaranteed by the design. 5 Non-EDO mode. 6 EDO mode, GPMI clock 100 MHz (AS=DS=DH=1, GPMI_CTL1 [RDN_DELAY] = 8, GPMI_CTL1 [HALF_PERIOD] = 0). In EDO mode (Figure 24), NF16/NF17 are different from the definition in non-EDO mode (Figure 23). They are called tREA/tRHOH (RE# access time/RE# HIGH to output hold). The typical values for them are 16 ns (max for tREA)/15 ns (min for tRHOH) at 50 MB/s EDO mode. In EDO mode, GPMI samples NAND_DATAxx at the rising edge of delayed NAND_RE_B provided by an internal DPLL. The delay value can be controlled by GPMI_CTRL1.RDN_DELAY (see the GPMI chapter of the i.MX 8M Mini Applications Processor Reference Manual [IMX8MMRM]). The typical value of this control register is 0x8 at 50 MT/s EDO mode. But if the board delay is big enough and cannot be ignored, the delay value should be made larger to compensate the board delay. i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 NXP Semiconductors 47 Electrical characteristics 3.9.4.2 Source synchronous mode AC timing (ONFI 2.x compatible) Figure 26 to Figure 28 show the write and read timing of Source Synchronous mode. NF18 NF19 .!.$?#%?" NAND_CLE NAND_ALE NAND_WE/RE_B NAND_CLK NF23 NF25 NF26 NF25 NF26 NF22 NF24 NAND_DQS NAND_DQS Output enable NAND_DATA[7:0] NF20 NF21 CMD NF20 NF21 ADD NAND_DATA[7:0] Output enable Figure 26. Source Synchronous mode command and address timing diagram i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 48 NXP Semiconductors .!.$?#%?" NF18 .!.$?#,% .!.$?!,% NAND_WE/RE_B .!.$?#,+ .!.$?$13 .!.$?$13 Output enable NF23 NF23 NF25 NF25 NF27 Electrical characteristics NF19 NF26 NF26 NF24 NF24 NF22 NF27 NF29 NF29 .!.$?$1;= .!.$?$1;= Output enable NF28 NF28 Figure 27. Source Synchronous mode data write timing diagram NF18 .!.$?#%?" .!.$?#,% NAND_ALE .!.$?7%2% .!.$?#,+ NF23 NF23 NF25 NF25 NF25 NF26 NF26 NF22 NF24 NF24 NF19 NF26 NF25 .!.$?$13 .!.$?$13 /UTPUTENABLE .!.$?$!4!;= .!.$?$!4!;= /UTPUTENABLE Figure 28. Source Synchronous mode data read timing diagram i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 NXP Semiconductors 49 Electrical characteristics .!.$?$13 NF30 .!.$?$!4!;= D0 D1 D2 D3 NF30 NF31 NF31 Figure 29. NAND_DQS/NAND_DQ read valid window Table 39. Source Synchronous mode timing parameters1 Timing ID Parameter Symbol T = GPMI Clock Cycle Unit Min. Max. NF18 NAND_CE0_B access time NF19 NAND_CE0_B hold time tCE CE_DELAY T - 0.79 [see note2] ns tCH 0.5 tCK - 0.63 [see note2] ns NF20 Command/address NAND_DATAxx setup time tCAS 0.5 tCK - 0.05 ns NF21 Command/address NAND_DATAxx hold time tCAH 0.5 tCK - 1.23 ns NF22 clock period NF23 preamble delay NF24 postamble delay tCK -- ns tPRE PRE_DELAY T - 0.29 [see note2] ns tPOST POST_DELAY T - 0.78 [see note2] ns NF25 NAND_CLE and NAND_ALE setup time tCALS 0.5 tCK - 0.86 ns NF26 NAND_CLE and NAND_ALE hold time tCALH 0.5 tCK - 0.37 ns NF27 NAND_CLK to first NAND_DQS latching transition tDQSS T - 0.41 [see note2] ns NF28 Data write setup -- 0.25 tCK - 0.35 NF29 Data write hold -- 0.25 tCK - 0.85 NF30 NAND_DQS/NAND_DQ read setup skew -- -- 2.06 NF31 NAND_DQS/NAND_DQ read hold skew -- -- 1.95 1 GPMI's Source Synchronous mode output timing can be controlled by the module's internal registers GPMI_TIMING2_CE_DELAY, GPMI_TIMING_PREAMBLE_DELAY, GPMI_TIMING2_POST_DELAY. This AC timing depends on these registers settings. In the table, CE_DELAY/PRE_DELAY/POST_DELAY represents each of these settings. 2 T = tCK(GPMI clock period) �0.075 ns (half of maximum p-p jitter). For DDR Source Synchronous mode, Figure 29 shows the timing diagram of NAND_DQS/NAND_DATAxx read valid window. The typical value of tDQSQ is 0.85 ns (max) and 1 ns (max) for tQHS at 200 MB/s. GPMI will sample NAND_DATA[7:0] at both rising and falling edge of an delayed NAND_DQS signal, which can be provided by an internal DPLL. The delay value can be controlled by GPMI register GPMI_READ_DDR_DLL_CTRL.SLV_DLY_TARGET (see the GPMI chapter of the i.MX 8M Mini Applications Processor Reference Manual [IMX8MMRM]). Generally, the typical delay value of this register is equal to 0x7 which means 1/4 clock cycle delay expected. But if the board delay is big enough and cannot be ignored, the delay value should be made larger to compensate the board delay. i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 50 NXP Semiconductors 3.9.4.3 ONFI NV-DDR2 mode (ONFI 3.2 compatible) Electrical characteristics 3.9.4.3.1 Command and address timing ONFI 3.2 mode command and address timing is the same as ONFI 1.0 compatible Async mode AC timing. See Section 3.9.4.1, Asynchronous mode AC timing (ONFI 1.0 compatible)," for details. 3.9.4.3.2 Read and write timing ONFI 3.2 mode read and write timing is the same as Toggle mode AC timing. See Section 3.9.4.4, Toggle mode AC Timing," for details. 3.9.4.4 Toggle mode AC Timing 3.9.4.4.1 Command and address timing NOTE Toggle mode command and address timing is the same as ONFI 1.0 compatible Asynchronous mode AC timing. See Section 3.9.4.1, Asynchronous mode AC timing (ONFI 1.0 compatible)," for details. 3.9.4.4.2 Read and write timing Figure 30. Toggle mode data write timing i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 NXP Semiconductors 51 Electrical characteristics DEV?CLK .!.$?#%X?" .!.$?#,% .& .!.$?!,% .!.$?7%?" .!.$?2%?" .!.$?$13 .!.$?$!4!;= T#+ .& T#+ T#+ .& T#+ T#+ Figure 31. Toggle mode data read timing Table 40. Toggle mode timing parameters Timing ID Parameter Symbol T = GPMI Clock Cycle Unit Min. Max. NF1 NAND_CLE setup time tCLS (AS + DS) T - 0.12 [see note1s,2] NF2 NAND_CLE hold time tCLH DH T - 0.72 [see note2] NF3 NAND_CE0_B setup time tCS (AS + DS) T - 0.58 [see notes,2] NF4 NAND_CE0_B hold time tCH DH T - 1 [see note2] NF5 NAND_WE_B pulse width tWP DS T [see note2] NF6 NAND_ALE setup time tALS (AS + DS) T - 0.49 [see notes,2] NF7 NAND_ALE hold time tALH DH T - 0.42 [see note2] NF8 Command/address NAND_DATAxx setup time tCAS DS T - 0.26 [see note2] NF9 Command/address NAND_DATAxx hold time tCAH DH T - 1.37 [see note2] NF18 NAND_CEx_B access time tCE CE_DELAY T [see notes3,2] -- ns NF22 clock period NF23 preamble delay tCK -- -- ns tPRE PRE_DELAY T [see notes4,2] -- ns i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 52 NXP Semiconductors Electrical characteristics Table 40. Toggle mode timing parameters (continued) Timing ID Parameter Symbol T = GPMI Clock Cycle Unit Min. Max. NF24 postamble delay tPOST POST_DELAY T + 0.43 [see -- ns note2] NF28 Data write setup tDS5 0.25 tCK - 0.32 -- ns NF29 Data write hold tDH5 0.25 tCK - 0.79 -- ns NF30 NAND_DQS/NAND_DQ read setup skew tDQSQ6 -- 3.18 ns NF31 NAND_DQS/NAND_DQ read hold skew tQHS6 -- 3.27 ns 1 AS minimum value can be 0, while DS/DH minimum value is 1. 2 T = tCK (GPMI clock period) -0.075 ns (half of maximum p-p jitter). 3 CE_DELAY represents HW_GPMI_TIMING2[CE_DELAY]. NF18 is guaranteed by the design. Read/Write operation is started with enough time of ALE/CLE assertion to low level. 4 PRE_DELAY+1 (AS+DS) 5 Shown in Figure 30. 6 Shown in Figure 31. For DDR Toggle mode, Figure 29 shows the timing diagram of NAND_DQS/NAND_DATAxx read valid window. The typical value of tDQSQ is 1.4 ns (max) and 1.4 ns (max) for tQHS at 133 MB/s. GPMI samples NAND_DATA[7:0] at both the rising and falling edges of a delayed NAND_DQS signal, which is provided by an internal DPLL. The delay value of this register can be controlled by the GPMI register GPMI_READ_DDR_DLL_CTRL.SLV_DLY_TARGET (see the GPMI chapter of the i.MX 8M Mini Applications Processor Reference Manual [IMX8MMRM]). Generally, the typical delay value is equal to 0x7, which means a 1/4 clock cycle delay is expected. But if the board delay is big enough and cannot be ignored, the delay value should be made larger to compensate the board delay. 3.9.5 I2C bus characteristics The Inter-Integrated Circuit (I2C) provides functionality of a standard I2C master and slave. The I2C is designed to be compatible with the I2C Bus Specification, version 2.1, by Philips Semiconductor (now NXP Semiconductors). 3.9.6 MIPI D-PHY timing parameters MIPI D-PHY electrical specifications are compliance. i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 NXP Semiconductors 53 Electrical characteristics Table 41. MIPI PHY worst power dissipation1 MODE Power consume on Power consume on Power consume on VDD_MIPI_0P9 (mW) VDD_MIPI_1P2 (mW) VDD_MIPI_1P8 (mW) Total power consume (mW) M4 on 226.1 4.1 S4 on 35.6 265.8 2.1 Gbps M4 on S4 off 164.7 4.03 28.6 197.33 M4 off 63.02 0 15.8 78.82 S4 on ULPS 4.26 0.0367 0.0584 4.36 1 M4 indicates MIPI DSI have 4 data lane enable (at least 1 clock lane enable). S4 indicates MIPI CSI have 4 data lane enable (at least 1 clock lane enable). 3.9.7 PCIe PHY parameters The PCIe interface is designed to be compatible with PCIe specification Gen2 x1 lane and supports the PCI Express 1.1/2.0 standard. Table 42. PCIe DC electrical characteristics Parameter Description Min PD Power Consumption Normal Gen2 -- Partial Mode -- Slumber Mode -- Full Powerdown -- Typ 129.5 98.2 4.9 0.1 Max Unit -- mW -- mW -- mW -- mW 3.9.7.1 PCIE_RESREF reference resistor connection The impedance calibration process requires connection of reference resistor 8.2 k 1% precision resistor on PCIE_RESREF pads to ground. It is used for termination impedance calibration. 3.9.8 PDM timing parameters Figure 32 illustrates the input timing of the PDM. i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 54 NXP Semiconductors Electrical characteristics PDM Clock PDM Bitstream ipg_clk_app Pulse right pre_channel_1 ipg_dee_clk Channel 1 Channel 0 Figure 32. PDM input timing PDM clock operative range is from 500 kHz to 6 MHz. Within range, only need to configure ipg_clk_app rate and CLKDIV without I/O timing concerns. 3.9.9 Pulse width modulator (PWM) timing parameters This section describes the electrical information of the PWM. The PWM can be programmed to select one of three clock signals as its source frequency. The selected clock signal is passed through a prescaler before being input to the counter. The output is available at the pulse-width modulator output (PWMO) external pin. Figure 33 depicts the timing of the PWM, and Table 43 lists the PWM timing parameters. 0 0 07-N?/54 Figure 33. PWM timing Table 43. PWM output timing parameters ID Parameter Min Max PWM Module Clock Frequency P1 PWM output pulse width high P2 PWM output pulse width low 0 66 (ipg_clk) 12 -- 12 -- Unit MHz ns ns i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 NXP Semiconductors 55 Electrical characteristics 3.9.10 FlexSPI timing parameters Measurements are with a load of 15 pF and an input slew rate of 1 V/ns. 3.9.10.1 FlexSPI input/read timing There are three sources for the internal sample clock for FlexSPI read data: � Dummy read strobe generated by FlexSPI controller and looped back internally (FlexSPIn_MCR0[RXCLKSRC] = 0x0) � Dummy read strobe generated by FlexSPI controller and looped back through the DQS pad (FlexSPIn_MCR0[RXCLKSRC] = 0x1) � Read strobe provided by memory device and input from DQS pad (FlexSPIn_MCR0[RXCLKSRC] = 0x3) The following sections describe input signal timing for each of these four internal sample clock sources. 3.9.10.1.1 SDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1 Table 44. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0 Symbol Parameter Min. Max. Unit Notes -- [D:] Frequency of operation -- 66 MHz -- F1 [D:] Setup time for incoming data 8.67 -- ns 1 F2 [D:] Hold time for incoming data 0 -- ns -- 1 The setup specification here assumes the data learning feature is not used. If data learning is enabled, then TIS can be decreased by up to 2ns. Table 45. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x1 Symbol Parameter Min. Max. Unit Notes -- [D:] Frequency of operation -- 133 MHz -- F1 [D:] Setup time for incoming data 1.5 -- ns 1 F2 [D:] Hold time for incoming data 1 -- ns -- 1 The setup specification here assumes the data learning feature is not used. If data learning is enabled, then TIS can be decreased by up to 2ns. FLEXSPI_SCLK FLEXSPI_DATA[7:0] Internal Sample Clock F1 F2 F1 F2 Figure 34. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1 i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 56 NXP Semiconductors Electrical characteristics NOTE Timing shown is based on the memory generating read data on the SCK falling edge, and FlexSPI controller sampling read data on the falling edge. 3.9.10.1.2 SDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x3 There are two cases when the memory provides both read data and the read strobe in SDR mode: � A1--Memory generates both read data and read strobe on SCK rising edge (or falling edge) � A2--Memory generates read data on SCK falling edge and generates read strobe on SCK rising edge Table 46. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case A1) Symbol Parameter Min. Max. Unit -- [D:] Frequency of operation -- 166 MHz F3 [D:] Time from SCK to data valid -- -- ns F4 [D:] Time from SCK to DQS -- -- ns -- [D:] Time delta between TSCKD and -2 2 ns TSCKDQS FLEXSPI_SCLK FLEXSPI_DATA[7:0] FLEXSPI_DQS F3 F3 F4 F4 Figure 35. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case A1) NOTE Timing shown is based on the memory generating read data and read strobe on the SCK rising edge. The FlexSPI controller samples read data on the DQS falling edge. Table 47. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case A2) Symbol Parameter Min. Max. Unit -- [D:] Frequency of operation -- 166 MHz F5 [D:] Time from SCK to data valid -- -- ns F6 [D:] Time from SCK to DQS -- -- ns -- [D:] Time delta between TSCKD and -2 2 ns TSCKDQS i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 NXP Semiconductors 57 Electrical characteristics FLEXSPI_SCLK FLEXSPI_DATA[7:0] FLEXSPI_DQS F5 F5 F5 F6 F6 F6 Internal Sample Clock Figure 36. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case A2) NOTE Timing shown is based on the memory generating read data on the SCK falling edge and read strobe on the SCK rising edge. The FlexSPI controller samples read data on a half-cycle delayed DQS falling edge. 3.9.10.1.3 DDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1 Table 48. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0 Symbol Parameter Min. Max. Unit Notes -- [D:] Frequency of operation -- 33 MHz -- F1 [D:] Setup time for incoming data 8.67 -- ns 1 F2 [D:] Hold time for incoming data 0 -- ns -- 1 The setup specification here assumes the data learning feature is not used. If data learning is enabled, then TIS can be decreased by up to 2ns. Table 49. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x1 Symbol Parameter Min. Max. Unit Notes -- [D:] Frequency of operation -- 66 MHz -- F1 [D:] Setup time for incoming data 1.5 -- ns 1 F2 [D:] Hold time for incoming data 1 -- ns -- 1 The setup specification here assumes the data learning feature is not used. If data learning is enabled, then TIS can be decreased by up to 2ns. SCLK SIO[0:7] Internal Sample Clocks F1 F2 F1 F2 Figure 37. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1 i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 58 NXP Semiconductors 3.9.10.1.4 DDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x3 Electrical characteristics Table 50. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case 1) Symbol Parameter Min. Max. Unit -- TSCKD TSCKDQS TSCKD - TSCKDQS [D:] Frequency of operation [D:] Time from SCK to data valid [D:] Time from SCK to DQS [D:] Time delta between TSCKD and TSCKDQS -- 166 MHz -- -- ns -- -- ns -0.6 0.6 ns SCK SIO[0:7] DQS TSCKD TSCKDQS Figure 38. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 3.9.10.2 FlexSPI output/write timing The following sections describe output signal timing for the FlexSPI controller including control signals and data outputs. 3.9.10.2.1 SDR mode -- TCK TDSO TDHO TCSS TCSH Symbol Table 51. FlexSPI output timing in SDR mode Parameter [D:] Frequency of operation1 [D:] SCK clock period [D:] Output data setup time [D:] Output data hold time [D:] Chip select output setup time [D:] Chip select output hold time Min. -- 6.02 2 2 3 x TCK - 1 3 x TCK - 1 Max. 166 -- -- -- -- -- Unit MHz ns ns ns ns ns i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 NXP Semiconductors 59 Electrical characteristics 1 The actual maximum frequency supported is limited by the FlexSPIn_MCR0[RXCLKSRC] configuration used. See the FlexSPI SDR input timing specifications. NOTE TCSS and TCSH are configured by the FlexSPIn_FLSHAxCR1 register, the default values are shown above. See the i.MX 8M Mini Applications Processor Reference Manual (IMX8MMRM) for more details. SCK TCSS CS SIO[0:7] TCK TDVO TDVO TDHO TDHO Figure 39. FlexSPI output timing in SDR mode 3.9.10.2.2 DDR mode TCSH Table 52. FlexSPI output timing in DDR mode Symbol Parameter Min. Max. Unit -- [D:] Frequency of operation1 -- 166 MHz TCK [D:] SCK clock period 6.02 -- ns TDSO [D:] Output data setup time -- 0.6 ns TDHO [D:] Output data hold time 0.6 -- ns TCSS [D:] Chip select output setup time 3 x TCK - 1.075 -- ns TCSH [D:] Chip select output hold time 3 x TCK - 1.075 -- ns 1 The actual maximum frequency supported is limited by the FlexSPIn_MCR0[RXCLKSRC] configuration used. See the FlexSPI SDR input timing specifications. NOTE TCSS and TCSH are configured by the FlexSPIn_FLSHAxCR1 register, the default values are shown above. See the i.MX 8M Mini Applications Processor Reference Manual (IMX8MMRM) for more details. i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 60 NXP Semiconductors Electrical characteristics SCK CS SIO[0:7] TCSS TCK TDVO TDHO TDVO TDHO TCSH Figure 40. FlexSPI output timing in DDR mode 3.9.11 SAI/I2S switching specifications This section provides the AC timings for the SAI in Master (clocks driven) and Slave (clocks input) modes. All timings are given for non inverted serial clock polarity (SAI_TCR[TSCKP] = 0, SAI_RCR[RSCKP] = 0) and non inverted frame sync (SAI_TCR[TFSI] = 0, SAI_RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal (SAI_BCLK) and/or the frame sync (SAI_FS) shown in the figures below. Table 53. Master mode SAI timing (50 MHz)1 Num Characteristic Min Max Unit S1 SAI_MCLK cycle time 20 S2 SAI_MCLK pulse width high/low 40% S3 SAI_BCLK cycle time 20 S4 SAI_BCLK pulse width high/low 40% S5 SAI_BCLK to SAI_FS output valid -- S6 SAI_BCLK to SAI_FS output invalid 0 S7 SAI_BCLK to SAI_TXD valid -- S8 SAI_BCLK to SAI_TXD invalid 0 S9 SAI_RXD/SAI_FS input setup before SAI_BCLK 2 S10 SAI_RXD/SAI_FS input hold after SAI_BCLK 0 1 To achieve 50 MHz for BCLK operation, clock must be set in feedback mode. -- 60% -- 60% 2 -- 2 -- -- -- ns MCLK period ns BCLK period ns ns ns ns ns ns Num S1 S2 S3 S4 S5 Table 54. Master mode SAI timing (25 MHz) Characteristic Min Max SAI_MCLK cycle time SAI_MCLK pulse width high/low SAI_BCLK cycle time SAI_BCLK pulse width high/low SAI_BCLK to SAI_FS output valid 40 40% 40 40% -- -- 60% -- 60% 2 Unit ns MCLK period ns BCLK period ns i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 NXP Semiconductors 61 Electrical characteristics Table 54. Master mode SAI timing (25 MHz) (continued) Num Characteristic Min Max S6 SAI_BCLK to SAI_FS output invalid 0 -- S7 SAI_BCLK to SAI_TXD valid -- 2 S8 SAI_BCLK to SAI_TXD invalid 0 -- S9 SAI_RXD/SAI_FS input setup before SAI_BCLK 12 -- S10 SAI_RXD/SAI_FS input hold after SAI_BCLK 0 -- Unit ns ns ns ns ns Figure 41. SAI timing--Master modes Table 55. Slave mode SAI timing (50 MHz)1 Num Characteristic Min Max S11 SAI_BCLK cycle time (input) S12 SAI_BCLK pulse width high/low (input) S13 SAI_FS input setup before SAI_BCLK S14 SAI_FA input hold after SAI_BCLK S17 SAI_RXD setup before SAI_BCLK S18 SAI_RXD hold after SAI_BCLK 1 TX does not support 50 MHz operation in Slave mode. 20 40% 2 2 2 2 -- 60% -- -- -- -- Num S11 S12 Table 56. Slave mode SAI timing (25 MHz) Characteristic Min SAI_BCLK cycle time (input) SAI_BCLK pulse width high/low (input) 40 40% Max -- 60% Unit ns BCLK period ns ns ns ns Unit ns BCLK period i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 62 NXP Semiconductors Num S13 S14 S15 S16 S17 S18 Electrical characteristics Table 56. Slave mode SAI timing (25 MHz) (continued) Characteristic Min Max Unit SAI_FS input setup before SAI_BCLK 12 -- ns SAI_FA input hold after SAI_BCLK 2 -- ns SAI_BCLK to SAI_TXD/SAI_FS output valid -- 7 ns SAI_BCLK to SAI_TXD/SAI_FS output invalid 0 -- ns SAI_RXD setup before SAI_BCLK 12 -- ns SAI_RXD hold after SAI_BCLK 2 -- ns Figure 42. SAI Timing -- Slave Modes 3.9.12 SPDIF timing parameters The Sony/Philips Digital Interconnect Format (SPDIF) data is sent using the bi-phase marking code. When encoding, the SPDIF data signal is modulated by a clock that is twice the bit rate of the data signal. Table 57 and Figure 43 and Figure 44 show SPDIF timing parameters for the Sony/Philips Digital Interconnect Format (SPDIF), including the timing of the modulating Rx clock (SPDIF_SR_CLK) for SPDIF in Rx mode and the timing of the modulating Tx clock (SPDIF_ST_CLK) for SPDIF in Tx mode. Table 57. SPDIF timing parameters Parameter Timing Parameter Range Symbol Unit Min Max SPDIF_IN Skew: asynchronous inputs, no specs apply -- -- SPDIF_OUT output (Load = 50 pf) � Skew � Transition rising � Transition falling -- -- -- -- -- -- 0.7 ns 1.5 ns 24.2 31.3 i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 NXP Semiconductors 63 Electrical characteristics Table 57. SPDIF timing parameters (continued) Parameter Timing Parameter Range Symbol Unit Min Max SPDIF_OUT output (Load = 30 pf) � Skew � Transition rising � Transition falling Modulating Rx clock (SPDIF_SR_CLK) period SPDIF_SR_CLK high period SPDIF_SR_CLK low period Modulating Tx clock (SPDIF_ST_CLK) period SPDIF_ST_CLK high period SPDIF_ST_CLK low period -- -- -- srckp srckph srckpl stclkp stclkph stclkpl -- -- -- 40.0 16.0 16.0 40.0 16.0 16.0 1.5 13.6 ns 18.0 -- ns -- ns -- ns -- ns -- ns -- ns SPDIF_SR_CLK (Output) srckpl VM srckp srckph VM Figure 43. SPDIF_SR_CLK timing diagram SPDIF_ST_CLK (Input) stclkpl VM stclkp stclkph VM Figure 44. SPDIF_ST_CLK timing diagram i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 64 NXP Semiconductors 3.9.13 UART I/O configuration and timing parameters Electrical characteristics 3.9.13.1 UART RS-232 I/O configuration in different modes The i.MX 8M Mini UART interfaces can serve both as DTE or DCE device. This can be configured by the DCEDTE control bit (default 0--DCE mode). Table 58 shows the UART I/O configuration based on the enabled mode. Table 58. UART I/O configuration vs. mode Port Direction DTE Mode Description Direction DCE Mode Description UARTx_RTS_B UARTx_CTS_B UARTx_TX_ DATA UARTx_RX_DATA Output Input Input Output UARTx_RTS_B from DTE to DCE UARTx_CTS_B from DCE to DTE Serial data from DCE to DTE Serial data from DTE to DCE Input Output Output Input UARTx_RTS_B from DTE to DCE UARTx_CTS_B from DCE to DTE Serial data from DCE to DTE Serial data from DTE to DCE 3.9.13.2 UART RS-232 Serial mode timing This section describes the electrical information of the UART module in the RS-232 mode. 3.9.13.2.1 UART transmitter Figure 45 depicts the transmit timing of UART in the RS-232 Serial mode, with 8 data bit/1 stop bit format. Table 59 lists the UART RS-232 Serial mode transmit timing characteristics. Possible UA1 UA1 Parity Bit Next Start Start UARTx_TX_DATA Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Par Bit STOP Bit (output) BIT UA1 UA1 Figure 45. UART RS-232 Serial mode transmit timing diagram Table 59. RS-232 Serial mode transmit timing parameters ID Parameter Symbol Min Max UA1 Transmit Bit Time tTbit 1/Fbaud_rate1 - Tref_clk2 1/Fbaud_rate + Tref_clk 1 Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16. 2 Tref_clk: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider). Unit -- i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 NXP Semiconductors 65 Electrical characteristics 3.9.13.2.2 UART receiver Figure 46 depicts the RS-232 Serial mode receive timing with 8 data bit/1 stop bit format. Table 60 lists Serial mode receive timing characteristics. UA2 UARTx_RX_DATA (output) Start Bit Bit 0 Bit 1 UA2 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Possible Parity Bit Bit 7 Par Bit STOP BIT Next Start Bit UA2 UA2 Figure 46. UART RS-232 Serial mode receive timing diagram Table 60. RS-232 Serial mode receive timing parameters ID Parameter Symbol Min Max Unit UA2 Receive Bit Time1 tRbit 1/Fbaud_rate2 - 1/(16 1/Fbaud_rate + -- x Fbaud_rate) 1/(16 x Fbaud_rate) 1 The UART receiver can tolerate 1/(16 x Fbaud_rate) tolerance in each bit. But accumulation tolerance in one frame must not exceed 3/(16 x Fbaud_rate). 2 Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16. 3.9.14 USB PHY parameters This section describes the USB-OTG PHY parameters. 3.9.14.1 Pad/Package/Board connections The USBx_VBUS pin cannot directly connect to the 5 V VBUS voltage on the USB2.0 link. Each USBx_VBUS pin must be isolated by an external 30 K1% precision resistor. The USB 2.0 PHY uses USBx_TXRTUNE and an external resistor to calibrate the USBx_DP/DN 45 source impedance. The external resistor value is 200 1% precision on each of USBx_TXRTUNE pad to ground. 3.9.14.2 USB PHY worst power consumption Table 61 shows the USB 2.0 PHY worst power dissipation. i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020 66 NXP Semiconductors Mode HS TX FS TX LS TX Suspend Sleep Electrical characteristics Table 61. USB 2.0 PHY worst power dissipation VDD_USB_0P8 VDD_USB_3P3 VD
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